Datasheet

ST10F269
153/184
Note: 1. Partially tested, guaranteed by design characterization.
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= -40 to +125°C, C
L
= 50pF,
ALE cycle time = 6 TCL + 2t
A
+ t
C
+ t
F
(187.5ns at
32MHz CPU clock without wait states).
Table 47 : Multiplexed Bus Characteristics (TQFP144 devices)
t
42
CC ALE fall. edge to RdCS, WrCS
(with RW delay)
7 + t
A
– TCL - 5.5+ t
A
–ns
t
43
CC ALE fall. edge to RdCS, WrCS
(no RW delay)
-5.5 + t
A
–-5.5 + t
A
–ns
t
44
CC Address float after RdCS,
WrCS (with RW delay) 1
–0 – 0ns
t
45
CC Address float after RdCS,
WrCS (no RW delay) 1
–12.5 – TCLns
t
46
SR RdCS to Valid Data In
(with RW delay)
–4 + t
C
– 2 TCL - 21 + t
C
ns
t
47
SR RdCS to Valid Data In
(no RW delay)
– 16.5 + t
C
– 3 TCL - 21 + t
C
ns
t
48
CC RdCS, WrCS Low Time
(with RW delay)
15.5 + t
C
– 2 TCL - 9.5 + t
C
–ns
t
49
CC RdCS, WrCS Low Time
(no RW delay)
28 + t
C
– 3 TCL - 9.5 + t
C
–ns
t
50
CC Data valid to WrCS 10 + t
C
– 2 TCL - 15+ t
C
–ns
t
51
SR Data hold after RdCS 0– 0 –ns
t
52
SR
Data float after RdCS
1
–16.5 + t
F
– 2 TCL - 8.5+t
F
ns
t
54
CC Address hold after
RdCS
, WrCS
6 + t
F
– 2 TCL - 19 + t
F
–ns
t
56
CC Data hold after WrCS 6 + t
F
– 2 TCL - 19 + t
F
–ns
Table 46 : Multiplexed Bus Characteristics (PQFP144 devices)
Symbol Parameter
Max. CPU Clock
= 40MHz
Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
min. max. min. max.
Symbol Parameter
Maximum CPU Clock =
32MHz
Variable CPU Clock
1/2 TCL = 1 to 32MHz
Unit
Minimum Maximum Minimum Maximum
t
5
CC
ALE high time 5.625 + t
A
– TCL - 10 + t
A
–ns
t
6
CC
Address setup to ALE 0.625 + t
A
–TCL - 15+ t
A
–ns
t
7
CC
Address hold after ALE
1
5.625 + t
A
– TCL - 10 + t
A
–ns
t
8
CC
ALE falling edge to RD
, WR
(with RW-delay)
5.625 + t
A
– TCL - 10 + t
A
–ns