Datasheet

ST10F269
152/184
21.4.10 - Multiplexed Bus
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= -40 to +125°C, C
L
= 50pF,
ALE cycle time = 6 TCL + 2t
A
+ t
C
+ t
F
(75ns at 40MHz CPU clock without wait states, PQFP144 devices).
Table 46 : Multiplexed Bus Characteristics (PQFP144 devices)
Symbol Parameter
Max. CPU Clock
= 40MHz
Variable CPU Clock
1/2 TCL = 1 to 40MHz
Unit
min. max. min. max.
t
5
CC ALE high time 4 + t
A
– TCL - 8.5 + t
A
–ns
t
6
CC Address setup to ALE 2 + t
A
– TCL - 10.5 + t
A
–ns
t
7
CC
Address hold after ALE
1
4 + t
A
– TCL - 8.5 + t
A
–ns
t
8
CC ALE falling edge to RD, WR
(with RW-delay)
4 + t
A
– TCL - 8.5 + t
A
–ns
t
9
CC ALE falling edge to RD, WR (no
RW-delay)
-8.5 + t
A
–-8.5 + t
A
–ns
t
10
CC Address float after RD, WR
(with RW-delay) 1
–6 – 6ns
t
11
CC Address float after RD, WR
(no RW-delay) 1
–18.5 – TCL + 6ns
t
12
CC RD, WR low time
(with RW-delay)
15.5 + t
C
– 2 TCL -9.5 + t
C
–ns
t
13
CC RD, WR low time
(no RW-delay)
28 + t
C
– 3 TCL -9.5 + t
C
–ns
t
14
SR RD to valid data in
(with RW-delay)
–6 + t
C
– 2 TCL - 19 + t
C
ns
t
15
SR RD to valid data in
(no RW-delay)
– 18.5 + t
C
– 3 TCL - 19 + t
C
ns
t
16
SR ALE low to valid data in – 18.5
+ t
A
+ t
C
– 3 TCL - 19
+ t
A
+ t
C
ns
t
17
SR Address/Unlatched CS to valid
data in
– 22 + 2t
A
+
t
C
– 4 TCL - 28
+ 2t
A
+ t
C
ns
t
18
SR Data hold after RD
rising edge
0– 0 –ns
t
19
SR
Data float after RD
1
–16.5 + t
F
– 2 TCL - 8.5 + t
F
ns
t
22
CC Data valid to WR 10 + t
C
– 2 TCL -15 + t
C
–ns
t
23
CC Data hold after WR 4 + t
F
– 2 TCL - 8.5 + t
F
–ns
t
25
CC ALE rising edge after RD, WR 15 + t
F
– 2 TCL -10 + t
F
–ns
t
27
CC Address/Unlatched CS hold
after RD
, WR
10 + t
F
– 2 TCL -15 + t
F
–ns
t
38
CC ALE falling edge to Latched CS -4 - t
A
10 - t
A
-4 - t
A
10 - t
A
ns
t
39
SR Latched CS low to Valid Data In – 18.5 + t
C
+
2t
A
– 3 TCL - 19
+ t
C
+ 2t
A
ns
t
40
CC Latched CS hold after RD, WR 27 + t
F
– 3 TCL - 10.5 + t
F
–ns