Datasheet

ST10F269
150/184
The real minimum value for TCL depends on the
jitter of the PLL. The PLL tunes f
CPU
to keep it
locked on f
XTAL
. The relative deviation of TCL is
the maximum when it is referred to one TCL
period. It decreases according to the formula and
to the Figure 69 given below. For N periods of TCL
the minimum value is computed using the
corresponding deviation D
N
:
where N = number of consecutive TCL periods
and 1 ≤ N ≤ 40. So for a period of 3 TCL periods
(N = 3):
D
3
= 4 - 3/15 = 3.8%
3TCL
min
=3TCL
NOM
x (1 - 3.8/100)
=3TCL
NOM
x 0.962
3TCL
min
= 36.075ns (at f
CPU
= 40MHz)
3TCL
min
= 45.1ns (at f
CPU
= 32MHz)
This is especially important for bus cycles using
wait states and e.g. for the operation of timers,
serial interfaces, etc. For all slower operations and
longer periods (e.g. pulse train generation or
measurement, lower Baud rates, etc.) the
deviation caused by the PLL jitter is negligible.
21.4.8 - External Clock Drive XTAL1
V
DD
= 5V ± 10%, V
SS
= 0V, T
A
= -40 to +125 °C (PQFP144 devices)
Notes: 1. Theoretical minimum. The real minimum value depends on the duty cycle of the input clock signal. 25MHz is the maximum input
frequency when using an external crystal oscillator. However, 40MHz can be applied with an external clock source.
2. The input clock signal must reach the defined levels V
IL
and V
IH2
.
TCL
MIN
TCL
NOM
1
D
N
100
×
D
N
4N15) %[]⁄(±
Figure 69 : Approximated Maximum PLL Jitter
Parameter Symbol
f
CPU
= f
XTAL
f
CPU
= f
XTAL
/ 2
f
CPU
= f
XTAL
x F
F = 1.5/2,/2.5/3/4/5
Unit
min max min max min max
Oscillator period t
OSC
SR
25
1
– 12.5 – 40 x N 100 x N ns
High time t
1
SR
10
2
–
5
2
–
10
2
–ns
Low time t
2
SR
10
2
–
5
2
–
10
2
–ns
Rise time t
3
SR –
3
2
–
3
2
–
3
2
ns
Fall time t
4
SR –
3
2
–
3
2
–
3
2
ns
3216
8
42
±1
±2
±3
±4
Max.jitter [%]
N
This approximated formula is valid for
1 ≤ N ≤ 40 and 10MHz ≤ f
CPU
≤ 40MHz