Datasheet

ST10F269
146/184
A complete conversion will take 14
CC
+ 2 t
SC
+ 4 TCL (fastest convertion rate = 6.06µs at 32MHz). This
time includes the conversion itself, the sample time and the time required to transfer the digital value to
the result register.
21.4 - AC characteristics
21.4.1 - Test Waveforms
21.4.2 - Definition of Internal Timing
The internal operation of the ST10F269 is
controlled by the internal CPU clock f
CPU
. Both
edges of the CPU clock can trigger internal (for
example pipeline) or external (for example bus
cycles) operations.
The specification of the external timing (AC
Characteristics) therefore depends on the time
Table 43 : ADC Sampling and Conversion Timing (TQFP144 devices)
ADCON.15/14
ADCTC
Conversion Clock t
CC
ADCON.13/12
ADSTC
Sample Clock t
SC
TCL = 1/2 x f
XTAL
At f
CPU
= 32MHz t
SC
=
At f
CPU
= 32MHz
and ADCTC = 00
00 TCL x 24 0.375µs00 t
CC
0.375µs
01 Reserved, do not use Reserved 01 t
CC
x 2 0.75µs
10 TCL x 96 1.5 µs10t
CC
x 4 1.50µs
11 TCL x 48 0.75 µs11t
CC
x 8 3.00µs
Figure 66 : Input / Output Waveforms
Figure 67 : Float Waveforms
2.4V
0.45V
Test Points
0.2V
DD
+0.9
0.2V
DD
+0.9
0.2V
DD
-0.1
0.2V
DD
-0.1
A
C inputs during testing are driven at 2.4V for a logic ‘1’ and 0.4V for a logic ‘0’.
T
iming measurements are made at V
IH
min for a logic ‘1’ and V
IL
max for a logic ‘0’.
Timing
Reference
Points
V
Load
+0.1V
V
Load
-0.1V
V
OH
-0.1V
V
OL
+0.1V
V
Load
V
OL
V
OH
For timing purposes a port pin is no longer floating when V
LOAD
changes of ±100mV.
It begins to float when a 100mV change from the loaded V
OH
/V
OL
level occurs (I
OH
/I
OL
= 20mA).