Datasheet

ST10F269
144/184
21.3.1 - A/D Converter Characteristics
V
DD
= 5V ± 10%, V
SS
= 0V T
A
= -40 to +85°C or -40 to +125°C, 4.0V ≤ V
AREF
≤ V
DD
+ 0.1V; V
SS
0.1V ≤
V
AGND
≤ V
SS
+ 0.2V
Notes: 1. V
AIN
may exceed V
AGND
or V
AREF
up to the absolute maximum ratings. However, the conversion result in these cases will be
X000h or X3FFh, respectively.
2. During the t
S
sample time the input capacitance C
ain
can be charged/discharged by the external source. The internal resistance of
the analog source must allow the capacitance to reach its final voltage level within the t
S
sample time. After the end of the t
S
sample
time, changes of the analog input voltage have no effect on the conversion result. Values for the t
SC
sample clock depend on the
programming. Referring to the t
C
conversion time formula of Section 21.3.2 - ‘Conversion Timing Control’ on page 145 and to
Table 42 on page 145:
- t
S
min. = 2 t
SC
min. = 2 t
CC
min. = 2 x 24 x TCL = 48 TCL
- t
S
max = 2 t
SC
max = 2 x 8 t
CC
max = 2 x 8 x 96 TCL = 1536 TCL
TCL is defined in Section 21.4.2 -, Section 21.4.4 -, and Section 21.4.5 - ‘Direct Drive’ on page 149:
3. The conversion time formula is:
- t
C
= 14 t
CC
+ t
S
+ 4 TCL (= 14 t
CC
+ 2 t
SC
+ 4 TCL)
The t
C
parameter includes the t
S
sample time, the time for determining the digital result and the time to load the result register with
the result of the conversion. Values for the t
CC
conversion clock depend on the programming. Referring to Table 42 on page 145:
- t
C
min. = 14 t
CC
min. + t
S
min. + 4 TCL = 14 x 24 x TCL + 48 TCL + 4 TCL = 388 TCL
- t
C
max = 14 t
CC
max + t
S
max + 4 TCL = 14 x 96 TCL + 1536 TCL + 4 TCL = 2884 TCL
4. This parameter is fixed by ADC control logic.
5. DNL, INL, TUE are tested at V
AREF
=5.0V, V
AGND
=0V, V
CC
= 4.9V. It is guaranteed by design characterization for all other
voltages within the defined voltage range.
‘LSB’ has a value of V
AREF
/ 1024.
The specified TUE is guaranteed only if an overload condition (see
OV
specification) occurs on maximum 2 not selected analog input
pins and the absolute sum of input overload currents on all analog input pins does not exceed 10mA.
6. The coupling factor is measured on a channel while an overload condition occurs on the adjacent not selected channel with an
absolute overload current less than 10mA.
7. Partially tested, guaranteed by design characterization.
8.To remove noise and undesirable high frequency components from the analog input signal, a low-pass filter must be connected at
the ADC input. The cut-off frequency of this filter should avoid 2 opposite transitions during the t
s
sampling time of the ST10 ADC:
- f
cut-off
≤ 1 / 5 t
s
to 1/10 t
s
where t
s
is the sampling time of the ST10 ADC and is not related to the Nyquist frequency determined by the t
c
conversion time.
Table 41 : A/D Converter Characteristics
Symbol Parameter Test Condition
Limit Values
Unit
minimum maximum
V
AREF
SR Analog Reference voltage 4.0 V
DD
+ 0.1 V
V
AIN
SR Analog input voltage
1 - 8
V
AGND
V
AREF
V
I
AREF
CC Reference supply current
running mode
power-down mode
7
–
–
500
1
µA
µA
C
AIN
CC ADC input capacitance
Not sampling
Sampling
7
–
–
10
15
pF
pF
t
S
CC Sample time
2 - 4
48 TCL 1 536 TCL
t
C
CC Conversion time
3 - 4
388 TCL 2 884 TCL
DNL CC Differential Nonlinearity
5
-0.5 +0.5 LSB
INL CC Integral Nonlinearity
5
-1.5 +1.5 LSB
OFS CC Offset Error
5
-1.0 +1.0 LSB
TUE CC Total unadjusted error
5
-2.0 +2.0 LSB
R
ASRC
SR Internal resistance of analog source t
S
in [ns]
2 - 7
–(t
S
/ 150) - 0.25 kΩ
K CC Coupling Factor between inputs
6 - 7
–1/500