Datasheet

ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW
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RP0H (F108h / 84h) ESFR Reset Value: --XXH
Notes: 1. RP0H.7 to RP0H.5 bits are loaded only during a long hardware reset. As pull-up resistors are active on each Port P0H pins
during reset, RP0H default value is "FFh".
2. These bits are set according to Port 0 configuration during any reset sequence.
3. RP0H is a read only register.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------- CLKSEL SALSEL CSSEL
WRC
R
1 - 2
R
2
R
2
R
2
WRC
2
Write Configuration Control
‘0’: Pin WR
acts as WRL, pin BHE acts as WRH
‘1’: Pins WR and BHE retain their normal function
CSSEL
2
Chip Select Line Selection (Number of active CS outputs)
0 0: 3 CS
lines: CS2...CS0
0 1: 2 CS
lines: CS1...CS0
1 0: No CS
line at all
1 1: 5 CS
lines: CS4...CS0 (Default without pull-downs)
SALSEL
2
Segment Address Line Selection (Number of active segment address outputs)
0 0: 4-bit segment address: A19...A16
0 1: No segment address lines at all
1 0: 8-bit segment address: A23...A16
1 1: 2-bit segment address: A17...A16 (Default without pull-downs)
CLKSEL
1 - 2
System Clock Selection
000: f
CPU
= 2.5 x f
OSC
001: f
CPU
= 0.5 x f
OSC
010: f
CPU
= 1.5 x f
OSC
011: f
CPU
= f
OSC
100: f
CPU
= 5 x f
OSC
101: f
CPU
= 2 x f
OSC
110: f
CPU
= 3 x f
OSC
111: f
CPU
= 4 x f
OSC