Datasheet
20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269
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BUSCON4 (FF1Ah / 8Dh) SFR Reset Value: 0000h
Notes: 1. BTYP (bit 6 and 7) are set according to the configuration of the bit l6 and l7 of PORT0 latched at the end of the reset sequence.
2. BUSCON0 is initialized with 0000h, if EA
pin is high during reset. If EA pin is low during reset, bit BUSACT0 and ALECTRL0 are
set (’1’) and bit field BTYP is loaded with the bus configuration selected via PORT0.
15 14 13 12 11 10 9 876 5 4 3210
CSWEN4 CSREN4 RDYPOL4 RDYEN4 - BUSACT4 ALECTL4 - BTYP MTTC4 RWDC4 MCTC
RW RW RW RW RW RW RW RW RW RW
MCTC Memory Cycle Time Control (Number of memory cycle time wait states)
0 0 0 0: 15 wait states (Nber = 15 - [MCTC])
. . .
1 1 1 1: No wait state
RWDCx Read/Write Delay Control for BUSCONx
‘0’: With read/write delay: activate command 1 TCL after falling edge of ALE
‘1’: No read/write delay: activate command with falling edge of ALE
MTTCx Memory Tristate Time Control
‘0’: 1 wait state
‘1’: No wait state
BTYP External Bus Configuration
0 0: 8-bit Demultiplexed Bus
0 1: 8-bit Multiplexed Bus
1 0: 16-bit Demultiplexed Bus
1 1: 16-bit Multiplexed Bus
Note: For BUSCON0, BTYP bit-field is defined via PORT0 during reset.
ALECTLx ALE Lengthening Control
‘0’: Normal ALE signal
‘1’: Lengthened ALE signal
BUSACTx Bus Active Control
‘0’: External bus disabled
‘1’: External bus enabled (within the respective address window, see
ADDRSEL)
RDYENx READY
Input Enable
‘0’: External bus cycle is controlled by bit field MCTC only
‘1’: External bus cycle is controlled by the READY
input signal
RDYPOLx Ready Active Level Control
‘0’: Active level on the READY
pin is low, bus cycle terminates with a ‘0’ on
READY pin,
‘1’: Active level on the READY
pin is high, bus cycle terminates with a ‘1’ on
READY
pin.
CSRENx Read Chip Select Enable
‘0’: The CS signal is independent of the read command (RD
)
‘1’: The CS signal is generated for the duration of the read command
CSWENx Write Chip Select Enable
‘0’: The CS
signal is independent of the write command (WR,WRL,WRH)
‘1’: The CS
signal is generated for the duration of the write command