Datasheet

ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW
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BUSCON0 (FF0Ch / 86h) SFR Reset Value: 0xx0h
BUSCON1 (FF14h / 8Ah) SFR Reset Value: 0000h
BUSCON2 (FF16h / 8Bh) SFR Reset Value: 0000h
BUSCON3 (FF18h / 8Ch) SFR Reset Value: 0000h
‘0’: Pins WR and BHE retain their normal function
‘1’: Pin WR
acts as WRL, pin BHE acts as WRH.
CLKEN System Clock Output Enable (CLKOUT)
‘0’: CLKOUT disabled: pin may be used for general purpose I/O
‘1’: CLKOUT enabled: pin outputs the system clock signal.
BYTDIS Disable/Enable Control for Pin BHE
(Set according to data bus width)
‘0’: Pin BHE
enabled
‘1’: Pin BHE
disabled, pin may be used for general purpose I/O.
ROMEN Internal Memory Enable (Set according to pin EA
during reset)
‘0’: Internal Memory disabled: accesses to the Memory area use the external bus
‘1’: Internal Memory enabled.
SGTDIS Segmentation Disable/Enable Control
‘0’: Segmentation enabled (CSP is saved/restored during interrupt entry/exit)
‘1’: Segmentation disabled (Only IP is saved/restored).
ROMS1 Internal Memory Mapping
‘0’: Internal Memory area mapped to segment 0 (00’0000H...00’7FFFH)
‘1’: Internal Memory area mapped to segment 1 (01’0000H...01’7FFFH).
STKSZ System Stack Size
Selects the size of the system stack (in the internal RAM) from 32 to 1024 words.
15 14 13 12 11 10 9 876 5 4 3210
CSWEN0 CSREN0 RDYPOL0 RDYEN0 - BUS ACT0 ALE CTL0 - BTYP MTTC0 RWDC0 MCTC
RW
RW RW
RW
RW
2
RW
2
RW
1
RW RW RW
15 14 13 12 11 10 9 876 5 4 3210
CSWEN1 CSREN1 RDYPOL1 RDYEN1 - BUSACT1 ALECTL1 - BTYP MTTC1 RWDC1 MCTC
RW RW RW RW RW RW RW RW RW RW
15 14 13 12 11 10 9 876 5 4 3210
CSWEN2 CSREN2 RDYPOL2 RDYEN2 - BUSACT2 ALECTL2 - BTYP MTTC2 RWDC2 MCTC
RW RW RW RW RW RW RW RW RW RW
15 14 13 12 11 10 9 876 5 4 3210
CSWEN3 CSREN3 RDYPOL3 RDYEN3 - BUSACT3 ALECTL3 - BTYP MTTC3 RWDC3 MCTC
RW RW RW RW RW RW RW RW RW RW