Datasheet

ST10F269 3 - FUNCTIONAL DESCRIPTION
13/184
3 - FUNCTIONAL DESCRIPTION
The architecture of the ST10F269 combines
advantages of both RISC and CISC processors
and an advanced peripheral subsystem. The
block diagram gives an overview of the different
on-chip components and the high bandwidth
internal bus structure of the ST10F269.
Figure 3 : Block Diagram
P4.7 CAN2_TXD
P4.6 CAN1_TXD
P4.5 CAN1_RXD
P4.4 CAN2_RXD
Port 0
Port 1Port 4
Port 6
Port 5
Port 3
Port 2
GPT1
GPT2
ASC usart
BRG
CPU-Core and MAC Unit
Internal
RAM
Watchdog
Interrupt Controller
8
32 16
PEC
16
16
CAN1
Port 7
Port 8
External Bus
10-Bit ADC
BRG
SSC
PWM
CAPCOM2
CAPCOM1
16
Oscillator
Controller
16
16
128K/256K Byte
and PLL
Flash Memory
XTAL1 XTAL2
2K Byte
16 15
8
8
8
16
3.3V Voltage
Regulator
10K Byte
XRAM
CAN2