Datasheet

19 - POWER REDUCTION MODES ST10F269
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Figure 62 : Simplified Powerdown Exit Circuitry
Figure 63 :
Powerdown Exit Sequence When Using an External Interrupt (PLL x 2)
DQ
Q
V
DD
enter
cd
external
interrupt
reset
stop pll
stop oscillator
V
DD
DQ
Q
cd
System clock
CPU and Peripherals clocks
RPD
V
DD
Pull-up
Weak Pull-down
(~ 200µA)
PowerDown
Q1
Q2
CPU clk
Internal
External
RPD
ExitPwrd
XTAL1
Interrupt
(internal)
~ 2.5 V
delay for oscillator/pll
stabilization
signal
Powerdown