Datasheet

18 - SYSTEM RESET ST10F269
120/184
Figure 59 : Minimum External Reset Circuitry
Figure 60 : External Reset Hardware Circuitry
Table 38 : PORT0 Latched Configuration for the Different Resets
Notes: 1. Not latched from PORT0.
2. Only RP0H low byte is used and the bit-fields are latched from PORT0 high byte to RP0H low byte.
X: Pin is sampled
-: Pin is not sampled
PORT0
Clock Options Seem. Add. Lines Chip Selects WR confide. Bus Type Reserved BSL Reserved Reserved Adapt Mode Emu Mode
Sample event
P0H.7 P0H.6 P0H.5 P0H.4 P0H.3 P0H.2 P0H.1 P0H.0 P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0
Software Reset - - -XXXXXXX- - - - - -
Watchdog Reset - - - X X X X X X X - - - - - -
Short Hardware Reset - - -XXXXXXXXXXXXX
Long Hardware Reset XXXXXXXXXXXXXXXX
Power-On Reset XXXXXXXXXXXXXXXX
Table 39 : PORT0 Bits Latched into the Different Registers After Reset
PORT0 bit
Nebr.
h7 h6 h5 h4 h3 h2 h1 h0 I7 I6 I5 I4 I3 I2 I1 I0
PORT0 bit
Name
CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC BUSTYP BUSTYP R BSL R R ADP EMU
RP0H
2
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
CLKCFG CLKCFG CLKCFG SALSEL SALSEL CSSEL CSSEL WRC
SYSCON X
1
X
1
X
1
X
1
X
1
X
1
BYTDIS
3
X
1
WRCFG
3
X
1
X
1
X
1
X
1
X
1
X
1
X
1
BUSCON0 X
1
X
1
X
1
X
1
-BUS
ACT0
4
ALE
CTL0
4
-BTYPBTYPX
1
X
1
X
1
X
1
X
1
X
1
Internal
Logic
To Clock Generator To Port 4 Logic To Port 6 Logic X
1
X
1
X
1
X
1
Internal X
1
X
1
Internal Internal
+
+
RSTOUT
RSTIN
RPD
C0
R0
V
DD
C1
External
Hardware
ST10F269
a) Manual hardware reset1
b) For automatic power-up and
a)b)
interruptible power-down mode
D2
RSTOUT
RSTIN
RPD
Open - drain
D1
+
C0
R0
V
DD
ST10F269
V
DD
External
Hardware
Inverter
+
C1
R1
V
DD
Reset Source
External
R2