Datasheet
18 - SYSTEM RESET ST10F269
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18 - SYSTEM RESET
System reset initializes the MCU in a predefined
state. There are five ways to activate a reset state.
The system start-up configuration is different for
each case as shown in Table 37.
Table 37 : Reset Event Definition
18.1 - Long Hardware Reset
The reset is triggered when RSTIN pin is pulled
low, then the MCU is immediately forced in reset
default state. It pulls low RSTOUT
pin, it cancels
pending internal hold states if any, it aborts
external bus cycle, it switches buses (data,
address and control signals) and I/O pin drivers to
high-impedance, it pulls high PORT0 pins and the
reset sequence starts.
To get a long hardware reset, the duration of the
external RSTIN
signal must be longer than 1040
TCL. The level of RPD pin is sampled during the
whole RSTIN
pulse duration. A low level on RPD
pin determines an asynchronous reset while a
high level leads to a synchronous reset.
Note A reset can be entered as synchronous
and exit as asynchronous if V
RPD
voltage
drops below the RPD pin threshold
(typically 2.5V for V
DD
= 5V) when RSTIN
pin is low or when RSTIN pin is internally
pulled low.
18.1.1 - Asynchronous Reset
Figure 54 and Figure 55 show asynchronous
reset condition (RPD pin is at low level).
Figure 54 : Asynchronous Reset Sequence External Fetch
Note: 1) RSTIN rising edge to internal latch of PORT0 is 3 CPU clock cycles (6 TCL) if the PLL is bypassed and the prescaler is on
(f
CPU
=f
XTAL
/ 2), else it is 4 CPU clock cycles (8 TCL).
Reset Source Short-cut Conditions
Power-on reset PONR Power-on
Long Hardware reset (synchronous & asynchronous)
LHWR t
RSTIN
> 1040 TCL
Short Hardware reset (synchronous reset)
SHWR 4 TCL < t
RSTIN
< 1038 TCL
Watchdog Timer reset WDTR WDT overflow
Software reset SWR SRST execution
6 or 8 TCL
1)
CPU Clock
RSTIN
Asynchronous
Reset Condition
RPD
RSTOUT
ALE
PORT0
Reset Configuration
1st Instruction External Fetch
Latching point of PORT0
for system start-up
configuration
81234 6759
RD
EXTERNAL FETCH
Internal reset
5 TCL