Datasheet

ST10F269 15 - CAN MODULES
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15 - CAN MODULES
The two integrated CAN modules (CAN1 and
CAN2) are identical and handle the completely
autonomous transmission and reception of CAN
frames according to the CAN specification V2.0
part B (active).
Each on-chip CAN module can receive and
transmit standard frames with 11-bit identifiers as
well as extended frames with 29-bit identifiers.
These two CAN modules are both identical to the
CAN module of the ST10F167.
Because of duplication of the CAN controllers, the
following adjustments are to be considered:
– Same internal register addresses of both CAN
controllers, but with base addresses differing in
address bit A8; separate chip select for each
CAN module. Refer to Chapter : Memory Organ-
ization on page 14.
– The CAN1 transmit line (CAN1_TxD) is the
alternate function of the Port P4.6 pin and the
receive line (CAN1_RxD) is the alternate
function of the Port P4.5 pin.
– The CAN2 transmit line (CAN2_TxD) is the
alternate function of the Port P4.7 pin and the
receive line (CAN2_RxD) is the alternate
function of the Port P4.4 pin.
– Interrupt request line of the CAN1 module is
connected to the XBUS interrupt line XP0,
interrupt of the CAN2 module is connected to
the line XP1.
– The CAN modules must be selected with
corresponding CANxEN bit of XPERCON register
before the bit XPEN of SYSCON register is set.
– The reset default configuration is: CAN1 is
enabled, CAN2 is disabled.
15.1 - CAN Modules Memory Mapping
15.1.1 - CAN1
Address range 00’EF00h - 00’EFFFh is reserved
for the CAN1 Module access. CAN1 is enabled by
setting XPEN bit 2 of the SYSCON register and by
setting bit 0 of the XPERCON register. Accesses
to the CAN Module use demultiplexed addresses
and a 16-bit data bus (Byte accesses are
possible). Two wait states give an access time of
125ns at 40MHz CPU clock or at 32MHz CPU
clock. No tri-state wait states are used.
15.1.2 - CAN2
Address range 00’EE00h - 00’EEFFh is reserved
for the CAN2 Module access. CAN2 is enabled by
setting XPEN bit 2 of the SYSCON register and by
setting bit 1 of the XPERCON register. Accesses
to the CAN Module use demultiplexed addresses
and a 16-bit data bus (Byte accesses are
possible). Two wait states give an access time of
125ns at 40MHz or 32MHz CPU clock. No tri-state
wait states are used.
Note: If one or both CAN modules is used,
Port 4 cannot be programmed to output all
8 segment address lines. Thus, only
4 segment address lines can be used,
reducing the external memory space to
5M Bytes (1M Byte per CS
line).
15.2 - CAN Bus Configurations
Depending on application, CAN bus configuration
may be one single bus with a single or multiple
interfaces or a multiple bus with a single or
multiple interfaces. The ST10F269 is able to
support these 2 cases.
Single CAN Bus
The single CAN Bus multiple interfaces
configuration may be implemented using 2 CAN
transceivers as shown in Figure 47.
Figure 47 : Single CAN Bus Multiple Interfaces,
Multiple Transceivers
CAN1
RxD
TxD
CAN2
RxD
TxD
CAN
Transceiver
CAN
Transceiver
CAN_H
CAN_H
CAN bus