ST10F269Zx 16-BIT MCU WITH MAC UNIT, 128K to 256K BYTE FLASH MEMORY AND 12K BYTE RAM DATASHEET ■ ■ 128K or 256KByte Flash Memory 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 10K Byte XRAM 16 16 8 16 Interrupt Controller 8 Por t 5 16 BRG BRG Port 3 Port 7 15 8 XTAL1 XTAL2 Voltage Regulator 3.
ST10F269 TABLE OF CONTENTS PAGE ST10F269 12345- 6- 7- 8- 2/184 Introduction ................................................................................................................. 6 Pin Data ...................................................................................................................... 7 Functional Description .............................................................................................. 13 Memory Organization ..........................................
ST10F269 TABLE OF CONTENTS 8.4 - 910 - 11 12 - PAGE EXCEPTION AND ERROR TRAPS LIST ..................................................................... 48 Capture/Compare (CAPCOM) Units ......................................................................... 49 General Purpose Timer Unit ..................................................................................... 52 10.1 - GPT1 ..................................................................................................................
ST10F269 TABLE OF CONTENTS PAGE 16 - Real Time Clock ..................................................................................................... 105 17 18 - 19 - 20 - 21 - 4/184 16.1 - RTC REGISTERS ....................................................................................................... 106 16.1.1 - RTCCON: RTC Control Register ................................................................. 106 16.1.2 - RTCPH & RTCPL: RTC PRESCALER Registers ................................
ST10F269 TABLE OF CONTENTS 21.4.7 21.4.8 21.4.9 21.4.10 21.4.11 21.4.12 21.4.13 21.4.14 - 22 23 - PAGE Phase Locked Loop ..................................................................................... 149 External Clock Drive XTAL1 ........................................................................ 150 Memory Cycle Variables ............................................................................. 151 Multiplexed Bus .........................................................................
1 - INTRODUCTION ST10F269 1 - INTRODUCTION The ST10F269 is a derivative of the STMicroelectronics ST10 family of 16-bit single-chip CMOS microcontrollers. It combines high CPU performance (up to 20 million instructions per second) with high peripheral functionality and enhanced I/O-capabilities. It also provides on-chip high-speed single voltage Flash memory, on-chip high-speed RAM, and clock generation via PLL. ST10F269 is processed in 0.35µm CMOS technology.
ST10F269 2 - PIN DATA 2 - PIN DATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 ST10F269 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P0H.0/AD8 P0L.7/AD7 P0L.6/AD6 P0L.5/AD5 P0L.4/AD4 P0L.3/AD3 P0L.2AD2 P0L.A/AD1 P0L.0/AD0 EA ALE READY WR/WRL RD V SS V DD P4.7A23/CAN2_TxD P4.6A22/CAN1_TxD P4.5A21/CAN1_RxD P4.4A20/CAN2_RxD P4.3/A19 P4.2/A18 P4.1/A17 P4.0/A16 RPD V SS V DD P3.
2 - PIN DATA ST10F269 Symbol Pin Type Function P6.0 - P6.7 1-8 I/O 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 6 outputs can be configured as push-pull or open drain drivers. The following Port 6 pins have alternate functions: 1 O P6.0 CS0 Chip Select 0 Output ... ... ... ... ... 5 O P6.4 CS4 Chip Select 4 Output 6 I P6.
ST10F269 2 - PIN DATA Symbol Pin Type Function P2.0 - P2.7 P2.8 - P2.15 47-54 57-64 I/O 16-bit bidirectional I/O port, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. Port 2 outputs can be configured as push-pull or open drain drivers. The input threshold of Port 2 is selectable (TTL or special). The following Port 2 pins have alternate functions: 47 I/O P2.
2 - PIN DATA Symbol P4.0 –P4.7 ST10F269 Pin Type Function 85-92 I/O Port 4 is an 8-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. The input threshold is selectable (TTL or special). Port 4.6 & 4.7 outputs can be configured as push-pull or open drain drivers.
ST10F269 Symbol 2 - PIN DATA Pin P0L.0 - P0L.7, 100-107, P0H.0 108, P0H.1 - P0H.7 111-117 Type Function I/O Two 8-bit bidirectional I/O ports P0L and P0H, bit-wise programmable for input or output via direction bit. Programming an I/O pin as input forces the corresponding output driver to high impedance state. In case of an external bus configuration, PORT0 serves as the address (A) and as the address / data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes.
2 - PIN DATA ST10F269 Symbol Pin Type VDD 46, 72, 82,93, 109, 126, 136, 144 - Digital Supply Voltage: = + 5V during normal operation and idle mode. VSS 18,45, 55,71, 83,94, 110, 127, 139, 143 - Digital Ground. DC1 DC2 56 17 - 3.3V Decoupling pin (2.7V on TQFP144 devices): a decoupling capacitor of ≥ 330 nF must be connected between this pin and nearest V SS pin.
ST10F269 3 - FUNCTIONAL DESCRIPTION 3 - FUNCTIONAL DESCRIPTION The architecture of the ST10F269 combines advantages of both RISC and CISC processors and an advanced peripheral subsystem. The block diagram gives an overview of the different on-chip components and the high bandwidth internal bus structure of the ST10F269. Figure 3 : Block Diagram 32 16 128K/256K Byte Flash Memory 2K Byte Internal RAM 16 CPU-Core and MAC Unit Watchdog 16 PEC 10K Byte XRAM Interrupt Controller 16 3.
4 - MEMORY ORGANIZATION ST10F269 4 - MEMORY ORGANIZATION The memory space of the ST10F269 is configured in a unified memory architecture. Code memory, data memory, registers and I/O ports are organized within the same linear address space of 16M Bytes. The entire memory space can be accessed Byte wise or Word wise. Particular portions of the on-chip memory have additionally been made directly bit addressable. Flash: 128K or 256K Bytes of on-chip Flash memory.
ST10F269 4 - MEMORY ORGANIZATION Figure 4 : ST10F269 On-chip Memory Mapping Segment 2 Segment 3 Segment 4 14 RAM, SFR and X-pheripherals are mapped into the address space.
4 - MEMORY ORGANIZATION ST10F269 XPERCON (F024h / 12h) ESFR Reset Value: - - 05h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - - - - RTCEN XRAM2EN XRAM1EN CAN2EN CAN1EN RW RW RW RW RW CAN1EN CAN1 Enable Bit ‘0’: Accesses to the on-chip CAN1 XPeripheral and its functions are disabled. P4.5 and P4.6 pins can be used as general purpose I/Os. Address range 00’EF00h-00’EFFFh is only directed to external memory if CAN2EN is also ‘0’.
ST10F269 5 - INTERNAL FLASH MEMORY 5 - INTERNAL FLASH MEMORY 5.1 - Overview – 128K or 256K Byte on-chip Flash memory – Two possibilities of Flash mapping into the CPU address space – Flash memory can be used for code and data storage – 32-bit, zero waitstate read access (50ns cycle time at fCPU = 40MHz on PQFP144 devices and 62.
5 - INTERNAL FLASH MEMORY Instructions and Commands All operations besides normal read operations are initiated and controlled by command sequences written to the Flash Command Interface (CI).
ST10F269 be temporarily unlocked for update (write) operations. With the two possibilities for write protection whole memory or block specific - a flexible installation of write protection is supported to protect the Flash memory or parts of it from unauthorized programming or erase accesses and to provide virus-proof protection for all system code blocks. All write protection also is enabled during boot operation.
5 - INTERNAL FLASH MEMORY ST10F269 Flash Status (see note for address) 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 FSB.7 FSB.6 FSB.5 R R R 4 3 2 1 0 - FSB.3 FSB.2 - - R R FSB.7 Flash Status bit 7: Data Polling Bit Programming Operation: this bit outputs the complement of the bit 7 of the word being programmed, and after completion, will output the bit 7 of the word programmed. Erasing Operation: outputs a ‘0’ during erasing, and ‘1’ after erasing completion.
ST10F269 5 - INTERNAL FLASH MEMORY 5.3.5 - Flash Protection Register The Flash Protection register is a non-volatile register that contains the protection status. This register can be read by using the Read Protection Status (RP) command, and programmed by using the dedicated Set Protection command.
5 - INTERNAL FLASH MEMORY the time-out is running; if FSB.3 is ‘1’, the time-out has expired and the EPC is erasing the block(s).
ST10F269 If the second command given is not an erase confirm or if the coded cycles are wrong, the instruction aborts, and the device is reset to Read Mode. It is not necessary to program the block with 0000h as the EPC will do this automatically before the erasing to FFFFh. Read operations after the EPC has started, output the Flash Status Register. During the execution of the erase by the EPC, the device accepts only the Erase Suspend and Read/Reset instructions. Data Polling bit FSB.
5 - INTERNAL FLASH MEMORY ST10F269 Protection Status will return the new PR value only after a reset. Block Temporary Unprotection (BTU). This Instruction can be used to temporary unprotect all the blocks from Program / Erase protection. The Unprotection is disabled after a Reset cycle. The Block Temporary Unprotection command xxC1h must be given to enable Block Temporary Unprotection. The Command must be preceded by the CI-Protection Enable cycles and followed by the Read/Reset command xxF0h.
ST10F269 5 - INTERNAL FLASH MEMORY Table 3 : Instructions Instruction Read/Reset Read/Reset 1st Cycle Mne Cycle RD RD 1+ 3+ PW 4 Block Erase BE 6 Chip Erase Erase Suspend Erase Resume CE ES ER 6 1 1 Set Block/Code Protection SP Read Protection Status RP 3rd Cycle 4 Code Temporary Unprotection CTU 1 Code Temporary Protection CTP 1 6th Cycle 7th Cycle Data xxF0h Addr.1 x1554h x2AA8h xxxxxh Data xxA8h xx54h xxF0h Addr.
5 - INTERNAL FLASH MEMORY ST10F269 8. MEM = any address inside the Flash memory space. Absolute addressing mode must be used (MOV MEM, Rn), and instruction must be executed from Flash memory space. 9. Odd word address = 4n-2 where n = 0, 1, 2, 3..., ex. 0002h, 0006h... – Generally, command sequences cannot be written to Flash by instructions fetched from the Flash itself. Thus, the Flash commands must be written by instructions, executed from internal RAM or external memory.
ST10F269 5 - INTERNAL FLASH MEMORY 5.5.2 - Basic Flash Access Control When accessing the Flash all command write addresses have to be located within the active Flash memory space. The active Flash memory space is that logical address range which is covered by the Flash after mapping. When using data page pointer (DPP) for addressing the Flash, make sure that address bit A15 and A14 of the command addresses are reflected in both LSBs of the selected data page pointer (A15 - DPPx.1 and A14 - DPPx.0).
5 - INTERNAL FLASH MEMORY ST10F269 5.5.3 - Programming Examples Most of the microcontroller programs are written in the C language where the data page pointers are automatically set by the compiler. But because the C compiler may use the not allowed direct addressing mode for Flash write addresses, it is necessary to program the organizational Flash accesses (command sequences) with assembler in-line routines which use indirect addressing.
ST10F269 5 - INTERNAL FLASH MEMORY ;R12 contains the segment offset address to be ;programmed ;R13 contains the data to be programmed EXTS R11, #1 ;use EXTended addressing for next MOV instruction MOV [R12], R13 ;command cycle 4: the EPC starts execution of ;Programming Command Data_Polling: EXTS R11, #1 ;use EXTended addressing for next MOV instruction MOV R7, [R12] ;read Flash Status register (FSB) in R7 MOV R6, R7 ;save it in R6 register ;Check if FSB.7 = Data.7 (i.e. R7.7 = R13.
5 - INTERNAL FLASH MEMORY ST10F269 Example 3 Performing the Block Erase command We assume that in the initialization phase the lowest 32K Bytes of Flash memory (sector 0) have been mapped to segment 1.The registers R11/R12 contain an address related to the block to be erased (segment number in R11, segment offset in R12, for example R11 = 01h, R12= 4000h will erase the block 1 - first 8K byte block).
ST10F269 5 - INTERNAL FLASH MEMORY .... 5.6 - Bootstrap Loader The built-in bootstrap loader (BSL) of the ST10F269 provides a mechanism to load the startup program through the serial interface after reset. In this case, no external memory or internal Flash memory is required for the initialization code starting at location 00’0000h (see Figure 5).
5 - INTERNAL FLASH MEMORY ST10F269 When the ST10F269 has entered BSL mode, the following configuration is automatically set (values that deviate from the normal reset values, are marked): Watchdog Timer: Disabled Register SYSCON: 0E00h Context Pointer CP: FA00h Register STKUN: FA40h Stack Pointer SP: FA40h Register STKOV: FA0Ch 0<->C Register S0CON: 8011h Register BUSCON0: acc. to startup configuration P3.10 / TXD0: ‘1’ Register S0BG: Acc. to ‘00’ Byte DP3.
ST10F269 5 - INTERNAL FLASH MEMORY Figure 7 : Memory Configuration after Reset Segment 16M Bytes Access to: 255 16M Bytes 255 external bus disabled 2 1 255 external bus enabled 2 1 0 depends on reset config EA, Port0 2 1 IRAM IRAM IRAM 0 internal Flash Flash enabled User Test Flash BSL mode active Access to: Segment 16M Bytes Access: Segment internal Flash Flash enabled User Test Flash 0 User Flash depends on reset config EA, Port0 Yes (P0L.4=’0’) Yes (P0L.4=’0’) No (P0L.
5 - INTERNAL FLASH MEMORY ST10F269 5.6.5 - Choosing the Baud Rate for the BSL The calculation of the serial Baud rate for ASC0 from the length of the first zero Byte that is received, allows the operation of the bootstrap loader of the ST10F269 with a wide range of Baud rates. However, the upper and lower limits have to be kept, in order to insure proper data transfer.
ST10F269 6 - CENTRAL PROCESSING UNIT (CPU) 6 - CENTRAL PROCESSING UNIT (CPU) The CPU uses a bank of 16 word registers to run the current context. This bank of General Purpose Registers (GPR) is physically stored within the on-chip Internal RAM (IRAM) area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU. The number of register banks is only restricted by the available Internal RAM space.
6 - CENTRAL PROCESSING UNIT (CPU) ST10F269 The System Configuration Register SYSCON This bit-addressable register provides general system configuration and control functions. The reset value for register SYSCON depends on the state of the PORT0 pins during reset.
ST10F269 6 - CENTRAL PROCESSING UNIT (CPU) 6.1.1 - Features 6.1.1.1 - Enhanced Addressing Capabilities – New addressing modes including a double indirect addressing mode with pointer post-modification. – Parallel Data Move: this mechanism allows one operand move during Multiply-Accumulate instructions without penalty. – New transfer instructions CoSTORE (for fast access to the MAC SFRs) and CoMOV (for fast memory to memory table transfer). 6.1.1.
6 - CENTRAL PROCESSING UNIT (CPU) ST10F269 6.2 - Instruction Set Summary The Table 4 lists the instructions of the ST10F269. The various addressing modes, instruction operation, parameters for conditional execution of instructions, opcodes and a detailed description of each instruction can be found in the “ST10 Family Programming Manual”.
ST10F269 6 - CENTRAL PROCESSING UNIT (CPU) Table 4 : Instruction Set Summary Mnemonic Description Bytes JNBS Jump relative and set bit if direct bit is not set 4 CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call absolute subroutine 4 TRAP Call interrupt service routine via immediate trap number 2 PUSH, POP Push/pop direct word register onto/f
6 - CENTRAL PROCESSING UNIT (CPU) Mnemonic ST10F269 Addressing Modes Repeatability CoMUL CoMULu CoMULus CoMULsu CoMULCoMULuCoMULusCoMULsu- Rwn, Rwm [IDXi⊗], [Rwm⊗] Rwn, [Rwm⊗] No No No Rwn, Rwm [IDXi⊗], [Rwm⊗] Rwn, [Rwm⊗] No Yes Yes Rwn, Rwm [IDXi⊗], [Rwn⊗] Rwn, [RWm⊗] No No No [Rwm⊗] Yes [IDXi⊗] Yes [IDXi⊗], [Rwm⊗] Yes - No Rwn, CoReg No [Rwn⊗], Coreg Yes [IDXi⊗], [Rwm⊗] Yes CoMUL, rnd CoMULu, rnd CoMULus, rnd CoMULsu, rnd CoMAC CoMACu CoMACus CoMACsu CoMACCoMACuCoMACusCoMACsuCoMA
ST10F269 6 - CENTRAL PROCESSING UNIT (CPU) Mnemonic Addressing Modes Repeatability CoMACM CoMACMu CoMACMus CoMACMsu CoMACMCoMACMuCoMACMusCoMACMsuCoMACM, rnd CoMACMu, rnd CoMACMus, rnd [IDXi⊗], [Rwm⊗] Yes Rwn, Rwm [IDXi⊗], [Rwm⊗] Rwn, [Rwm⊗] No Yes Yes Rwn, Rwm [IDXi⊗], [Rwm⊗] Rwn, [Rwm⊗] No Rwm #data4 [Rwm⊗] Yes No Yes Rwn, Rwm [IDXi⊗], [Rwm⊗] Rwn, [Rwm⊗] No No No CoMACMsu, rnd CoMACMR CoMACMRu CoMACMRus CoMACMRsu CoMACMR, rnd CoMACMRu, rnd CoMACMRus, rnd CoMACMRsu, rnd CoADD CoADD2 CoSUB Co
6 - CENTRAL PROCESSING UNIT (CPU) ST10F269 The Table 5 shows the various combinations of pointer post-modification for each of these 2 new addressing modes. In this document the symbols “[Rwn⊗]” and “[IDXi⊗]” refer to these addressing modes.
ST10F269 7 - EXTERNAL BUS CONTROLLER 7 - EXTERNAL BUS CONTROLLER All of the external memory accesses are performed by the on-chip external bus controller.
7 - EXTERNAL BUS CONTROLLER ST10F269 Figure 11 : Chip Select Delay Normal Demultiplexed Segment (P4) ALE Lengthen Demultiplexed Bus Cycle Bus Cycle Address (P1) ALE Normal CSx Unlatched CSx Data Data BUS (P0) RD Data BUS (P0) Data WR 44/184 Read/Write Read/Write Delay Delay
ST10F269 8 - INTERRUPT SYSTEM 8 - INTERRUPT SYSTEM The interrupt response time for internal program execution is from 125ns to 300ns at 40MHz CPU clock on PQFP144 devices and 156.25ns to 375ns at 32MHz of CPU clock on TQFP144 devices. The ST10F269 architecture supports several mechanisms for fast and flexible response to service requests that can be generated from various sources (internal or external) to the microcontroller.
8 - INTERRUPT SYSTEM ST10F269 8.
ST10F269 8 - INTERRUPT SYSTEM Table 7 : Interrupt Sources (continued) Source of Interrupt or PEC Service Request Request Flag Enable Flag Interrupt Vector Vector Location Trap Number CAPCOM Timer 1 T1IR T1IE T1INT 00’0084h 21h CAPCOM Timer 7 T7IR T7IE T7INT 00’00F4h 3Dh CAPCOM Timer 8 T8IR T8IE T8INT 00’00F8h 3Eh GPT1 Timer 2 T2IR T2IE T2INT 00’0088h 22h GPT1 Timer 3 T3IR T3IE T3INT 00’008Ch 23h GPT1 Timer 4 T4IR T4IE T4INT 00’0090h 24h GPT2 Timer 5 T5IR T5IE T
8 - INTERRUPT SYSTEM ST10F269 xxIC (yyyyh / zzh) SFR Area Reset Value: - - 00h 15 14 13 12 11 10 9 8 7 6 - - - - - - - - xxIR xxIE ILVL GLVL RW RW RW RW Bit 5 4 3 2 1 0 Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests.
ST10F269 9 - CAPTURE/COMPARE (CAPCOM) UNITS 9 - CAPTURE/COMPARE (CAPCOM) UNITS The ST10F269 has two 16 channels CAPCOM units as described in Figure 12. These support generation and control of timing sequences on up to 32 channels with a maximum resolution of 200ns at 40MHz CPU clock on PQFP144 devices and 250ns at 32MHz CPU clock on TQFP144 devices.
9 - CAPTURE/COMPARE (CAPCOM) UNITS ST10F269 * The CAPCOM2 unit provides 16 capture inputs, but only 12 compare outputs. CC24I to CC27I are inputs only.
ST10F269 9 - CAPTURE/COMPARE (CAPCOM) UNITS Table 9 : Compare Modes Compare Modes Function Mode 0 Interrupt-only compare mode; several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match; several compare events per timer period are possible Mode 2 Interrupt-only compare mode; only one compare interrupt per timer period is generated Mode 3 Pin set ‘1’ on match; pin reset ‘0’ on compare time overflow; only one compare event per timer period is generated Double
10 - GENERAL PURPOSE TIMER UNIT ST10F269 10 - GENERAL PURPOSE TIMER UNIT The GPT unit is a flexible multifunctional timer/ counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2.
ST10F269 10 - GENERAL PURPOSE TIMER UNIT Table 13 : GPT1 Timer Input Frequencies, Resolution and Periods (TQFP144 devices) Timer Input Selection T2I / T3I / T4I fCPU = 32MHz 000b 001b 010b 011b 100b 101b 110b 111b 8 16 32 64 128 256 512 1024 Input Freq 4MHz 2MHz 1MHz 500KHz 250KHz 125KHz 62.5KHz 31.125KHz Resolution 250ns 500ns 1µs 2µs 4µs 8µs 16µs 32µs Period maximum 16.4ms 32.8ms 65.5ms 131ms 262.1ms 524.3ms 1.05s 2.
10 - GENERAL PURPOSE TIMER UNIT ST10F269 Resolution and Period (TQFP144 devices) list the timer input frequencies, resolution and periods for each pre-scaler option at 40MHz (or 32MHz) CPU clock. This also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in Timer and Gated Timer Mode.
ST10F269 10 - GENERAL PURPOSE TIMER UNIT Figure 16 : Block Diagram of GPT2 T5EUD U/D CPU Clock 2n n=2...9 T5IN T5 Mode Control Interrupt Request GPT2 Timer T5 Clear Capture Interrupt Request CAPIN GPT2 CAPREL Reload T6IN CPU Clock T6EUD 2n n=2...
11 - PWM MODULE ST10F269 11 - PWM MODULE The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centre-aligned PWM. In addition, the PWM module can generate PWM burst signals and single shot outputs. Table 16 and Table 17 show the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM module can generate interrupt requests.
ST10F269 12 - PARALLEL PORTS 12 - PARALLEL PORTS 12.1 - Introduction The ST10F269 MCU provides up to 111 I/O lines with programmable features. These capabilities bring very flexible adaptation of this MCU to wide range of applications.
/184 - - - P0H - - P1H - - - E DP1H E - - - P8 - - - Y E - - P2LIN P2HIN P3LIN P3HIN P4LIN P6LIN (to be implemented) P7LIN P8LIN - - - Y Y Y Y Y Y Y Y - - - Y Y Y Y Y Y Y Y - - - Y Y Y Y Y Y Y Y DP8 DP7 - - - - - - - - : Bit has an I/O function : Bit has no I/O dedicated function or is not implemented : Register belongs to ESFR area PICON: - - - DP6 P7 - - - - Y Y Y Y Y Y Y Y ODP6 - - - - - - - - - - - - - - - - - - - - - Y Y Y Y Y Y Y Y - -
ST10F269 12 - PARALLEL PORTS 12.2.2 - Input Threshold Control 12.2 - I/O’s Special Features The standard inputs of the ST10F269 determine the status of input signals according to TTL levels. In order to accept and recognize noisy signals, CMOS-like input thresholds can be selected instead of the standard TTL thresholds for all pins of Port 2, Port 3, Port 4, Port 7 and Port 8.
12 - PARALLEL PORTS ST10F269 Figure 20 : Hysteresis for Special Input Thresholds Hysteresis Input level Bit state 12.2.3 - Output Driver Control The port output control registers POCONx allow to select the port output driver characteristics of a port. The aim of these selections is to adapt the output drivers to the application’s requirements, and to improve the EMI behaviour of the device. Two characteristics may be selected: Edge characteristic defines the rise/fall time for the respective output.
ST10F269 12 - PARALLEL PORTS The table lists the defined POCON registers and the allocation of control bit-fields and port pins. Table 18 : Port Control Register Allocation Control Register Controlled Port Nibble Physical Address 8-bit Address POCON0L F080h 40h P0L.7...4 P0L.3...0 POCON0H F082h 41h P0H.7...4 P0H.3...0 POCON1L F084h 42h P1L.7...4 P1L.3...0 POCON1H F086h 43h P1H.7...4 P1H.3...0 POCON2 F088h 44h P2.15...12 P2.11...8 P2.7...4 P2.3...0 POCON3 F08Ah 45h P3.
12 - PARALLEL PORTS 12.2.4 - Alternate Port Functions Each port line has one associated programmable alternate input or output function. – PORT0 and PORT1 may be used as address and data lines when accessing external memory. – Port 2, Port 7 and Port 8 are associated with the capture inputs or compare outputs of the CAPCOM units and/or with the outputs of the PWM module. Port 2 is also used for fast external interrupt inputs and for timer 7 input.
ST10F269 12 - PARALLEL PORTS 12.3 - PORT0 The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0, respectively. Both halves of PORT0 can be written (via a PEC transfer) without effecting the other half. P0L (FF00h / 80h) If this port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction registers DP0H and DP0L.
12 - PARALLEL PORTS ST10F269 12.3.1 - Alternate Functions of PORT0 When an external bus is enabled, PORT0 is used as data bus or address/data bus. Note that an external 8-bit demultiplexed bus only uses P0L, while P0H is free for I/O (provided that no other bus mode is enabled). PORT0 is also used to select the system start-up configuration. During reset, PORT0 is configured to input, and each line is held high through an internal pull-up device.
ST10F269 12 - PARALLEL PORTS When an external bus mode is enabled, the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware. The input of the port output Buffer is disconnected from the internal bus and is switched to the line labeled “Alternate Data Output” via a multiplexer. The alternate data can be the 16-bit intra-segment address or the 8/16-bit data information.
12 - PARALLEL PORTS ST10F269 12.4 - PORT1 The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1, respectively. Both halves of PORT1 can be written (via a PEC transfer) without effecting the other half. If this port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction registers DP1H and DP1L.
ST10F269 12 - PARALLEL PORTS Figure 23 : PORT1 I/O and Alternate Functions Alternate Function P1H PORT1 P1L a) b) P1H.7 P1H.6 P1H.5 P1H.4 P1H.3 P1H.2 P1H.1 P1H.0 P1L.7 P1L.6 P1L.5 P1L.4 P1L.3 P1L.2 P1L.1 P1L.
12 - PARALLEL PORTS ST10F269 12.5 - Port 2 If this 16-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP2. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP2. P2 (FFC0h / E0h) 15 14 SFR 13 12 11 10 9 P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 RW RW RW P2.y RW RW RW RW Reset Value: 0000h 8 7 6 5 4 3 2 1 0 P2.8 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.
ST10F269 12 - PARALLEL PORTS the output latch is clocked by the signal “Compare Trigger”. The direction of the pin should be set to output by the user, otherwise the pin will be in the high-impedance state and will not reflect the state of the output latch. As can be seen from the port structure in Figure 26, the user software always has free access to the port pin even when it is used as a compare output.
12 - PARALLEL PORTS ST10F269 Figure 25 : Port 2 I/O and Alternate Functions Alternate Function Port 2 P2.15 P2.14 P2.13 P2.12 P2.11 P2.10 P2.9 P2.8 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.
ST10F269 12 - PARALLEL PORTS The pins of Port 2 combine internal bus data with alternate data output before the port latch input. Figure 26 : Block Diagram of a Port 2 Pin Write ODP2.y Open Drain Latch Read ODP2.y Write DP2.y Internal Bus Direction Latch Read DP2.y 1 Alternate Data Output Output Latch MUX Output Buffer 0 Write Port P2.y P2.y CCyIO EXxIN ≥1 Compare Trigger Read P2.y Clock 1 MUX 0 Alternate Data Input Fast External Interrupt Input 12.
12 - PARALLEL PORTS ST10F269 (pins P3.15, P3.14 and P3.12 do not support open drain mode). P3 (FFC4h / E2h) 15 14 P3.15 - RW RW SFR 13 12 11 10 9 P3.13 P3.12 P3.11 P3.10 P3.9 RW P3.y Due to pin limitations register bit P3.14 is not connected to an output pin. RW RW RW RW Reset Value: 0000h 8 7 6 5 4 3 2 1 0 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.
ST10F269 12 - PARALLEL PORTS 12.6.1 - Alternate Functions of Port 3 The pins of Port 3 serve for various functions which include external timer control lines, the two serial interfaces and the control lines BHE/WRH and CLKOUT. Table 20 : Port 3 Alternative Functions Port 3 Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P3.
12 - PARALLEL PORTS ST10F269 When the on-chip peripheral associated with a Port 3 pin is configured to use both the alternate input and output function, the descriptions above apply to the respective current operating mode. The direction must be set accordingly. Port 3 pins with alternate input/output functions are: MTSR, MRST, RxD0 and SCLK. Note: Enabling the CLKOUT function automatically enables the P3.15 output driver. Setting bit DP3.15=’1’ is not required.
ST10F269 12 - PARALLEL PORTS possibility to program any port latches before. Thus, the appropriate alternate function is selected automatically. If BHE/WRH is not used in the system, this pin can be used for general purpose I/O by disabling the alternate function (BYTDIS = ‘1’ / WRCFG=’0’). Pin P3.12 (BHE/WRH) is another pin with an alternate output function, however, its structure is slightly different. After reset the BHE or WRH function must be used depending on the system start-up configuration.
12 - PARALLEL PORTS ST10F269 12.7 - Port 4 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP4. P4 (FFC8h / E4h) SFR Reset Value: --00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 RW RW RW RW RW RW RW RW P4.
ST10F269 12 - PARALLEL PORTS The number of segment address lines is selected via PORT0 during reset. The selected value can be read from bitfield SALSEL in register RP0H (read only) in order to check the configuration during run time. The CAN interfaces use 2 or 4 pins of Port 4 to interface each CAN Modules to an external CAN transceiver. In this case the number of possible segment address lines is reduced.
12 - PARALLEL PORTS ST10F269 Figure 31 : Block Diagram of a Port 4 Pin Write DP4.y “1” 1 MUX Direction Latch 0 Read DP4.y Internal Bus Alternate Function Enable Write P4.y Alternate Data Output Port Output Latch 1 P4.y MUX Output Buffer 0 Read P4.y Clock 1 MUX 0 78/184 Input Latch y = 7...
ST10F269 12 - PARALLEL PORTS Figure 32 : Block Diagram of P4.4 and P4.5 Pins Write DP4.x “1” 1 “0” MUX Direction Latch 1 MUX 0 0 Internal Bus Read DP4.x “0” 1 Alternate Function Enable 0 Write P4.x MUX Alternate Data Output Port Output Latch 1 P4.x MUX 0 Output Buffer Read P4.x Clock 1 MUX 0 CANy.RxD Input Latch & XPERCON.a (CANyEN) XPERCON.
12 - PARALLEL PORTS ST10F269 Figure 33 : Block Diagram of P4.6 and P4.7 Pins Write ODP4.x Open Drain Latch 1 MUX Read ODP4.x "0" 0 Write DP4.x 1 "1" 1 "1" MUX MUX Internal Bus Direction Latch 0 0 Read DP4.x 1 "0" Write P4.x MUX Alternate Function Enable 0 Alternate Data Output 1 1 MUX Port Output Latch MUX 0 0 Output Buffer Read P4.x P4.x Clock 1 MUX Input Latch 0 CANy.TxD Data output XPERCON.
ST10F269 12 - PARALLEL PORTS shall be used as analog inputs. Some pins of Port 5 also serve as external timer control lines for GPT1 and GPT2. 12.8.1 - Alternate Functions of Port 5 Each line of Port 5 is also connected to one of the multiplexer of the Analog/Digital Converter. All port lines (P5.15...P5.0) can accept analog signals (AN15...AN0) to be converted by the ADC. No special programming is required for pins that The Table 22 summarizes the alternate functions of Port 5.
12 - PARALLEL PORTS ST10F269 Port 5 pins have a special port structure (see Figure 35), first because it is an input only port, and second because the analog input channels are directly connected to the pins rather than to the input latches. Figure 35 : Block Diagram of a Port 5 Pin Internal Bus Channel Select Analog Switch to Sample + Hold Circuit P5.y/ANy Read Port P5.y Clock Input Latch Read Buffer y = 15...0 12.8.
ST10F269 12 - PARALLEL PORTS DP6.y Port Direction Register DP6 Bit y DP6.y = 0: Port line P6.y is an input (high impedance) DP6.y = 1: Port line P6.y is an output ODP6 (F1CEH / E7H) ESFR 15 14 13 12 11 10 9 8 - - - - - - - - 7 5 4 3 2 1 0 ODP6.7 ODP6.6 ODP6.5 ODP6.4 ODP6.3 ODP6.2 ODP6.1 ODP6.0 RW ODP6.y 6 Reset Value: --00h RW RW RW RW RW RW RW Port 6 Open Drain Control Register Bit y ODP6.y = 0: Port line P6.y output driver in push-pull mode ODP6.y = 1: Port line P6.
12 - PARALLEL PORTS ST10F269 The chip select lines of Port 6 have an internal weak pull-up device. This device is switched on during reset. This feature is implemented to drive the chip select lines high during reset in order to avoid multiple chip selection. After reset the CS function must be used, if selected so. In this case there is no possibility to program any port latches before. Thus the alternate function (CS) is selected automatically in this case.
ST10F269 12 - PARALLEL PORTS Figure 38 : Block Diagram of Pin P6.5 (HOLD) Write ODP6.5 Open Drain Latch Read ODP6.5 Internal Bus Write DP6.5 Direction Latch Read DP6.5 Write P6.5 Port Output Latch P6.5/HOLD Output Buffer Read P6.
12 - PARALLEL PORTS ST10F269 12.10 - Port 7 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP7. Each port line can be switched into push-pull or open drain mode via the open drain control register ODP7. P7 (FFD0h / E8h) SFR Reset Value: --00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - P7.7 P7.6 P7.5 P7.4 P7.3 P7.2 P7.1 P7.0 RW RW RW RW RW RW RW RW P7.
ST10F269 12 - PARALLEL PORTS 12.10.1 - Alternate Functions of Port 7 The upper 4 lines of Port 7 (P7.7...P7.4) serve as capture inputs or compare outputs (CC31IO...CC28IO) for the CAPCOM2 unit. The usage of the port lines by the CAPCOM unit, its accessibility via software and the precautions are the same as described for the Port 2 lines. As all other capture inputs, the capture input function of pins P7.7...P7.
12 - PARALLEL PORTS ST10F269 The structure of Port 7 differs in the way the output latches are connected to the internal bus and to the pin driver. Pins P7.3...P7.0 (POUT3...POUT0) EXOR the alternate data output with the port latch output, which allows to use the alternate data directly or inverted at the pin driver. Figure 40 : Block Diagram of Port 7 Pins P7.3...P7.0 Write ODP7.y Open Drain Latch Read ODP7.y Write DP7.y Internal Bus Direction Latch Read DP7.y Alternate Data Output Write DP7.
ST10F269 12 - PARALLEL PORTS Figure 41 : Block Diagram of Port 7 Pins P7.7...P7.4 Write ODP7.y Open Drain Latch Read ODP7.y Write DP7.y Internal Bus Direction Latch Read DP7.y 1 Alternate Data Output Output Latch MUX Output Buffer 0 Write Port P7.y Compare Trigger P7.y CCzIO ≥1 Read P7.y Clock 1 MUX 0 Input Latch Alternate Latch Data Input Alternate Pin Data Input y = (4...7) z = (28...
12 - PARALLEL PORTS ST10F269 corresponding direction register DP8. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP8. 12.11 - Port 8 If this 8-bit port is used for general purpose I/O, the direction of each line can be configured via the P8 (FFD4h / EAh) SFR Reset Value: --00h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - P8.7 P8.6 P8.5 P8.4 P8.3 P8.2 P8.1 P8.0 RW RW RW RW RW RW RW RW P8.
ST10F269 12 - PARALLEL PORTS 12.11.1 - Alternate Functions of Port 8 The 8 lines of Port 8 serve as capture inputs or as compare outputs (CC23IO...CC16IO) for the CAPCOM2 unit. The usage of the port lines by the CAPCOM unit, its accessibility via software and the precautions are the same as described for the Port 2 lines. As all other capture inputs, the capture input function of pins P8.7...P8.
12 - PARALLEL PORTS ST10F269 The structure of Port 8 differs in the way the output latches are connected to the internal bus and to the pin driver (see Figure 43). Pins P8.7...P8.0 (CC23IO...CC16IO) combine internal bus data and alternate data output before the port latch input, as do the Port 2 pins. Figure 43 : Block Diagram of Port 8 Pins P8.7...P8.0 Write ODP8.y Open Drain Latch Read ODP8.y Write DP8.y Internal Bus Direction Latch Read DP8.
ST10F269 13 - A/D CONVERTER 13 - A/D CONVERTER A 10-bit A/D converter with 16 multiplexed input channels and a sample and hold circuit is integrated on-chip. The sample time (for loading the capacitors) and the conversion time is programmable and can be adjusted to the external circuitry. To remove high frequency components from the analog input signal, a low-pass filter must be connected at the ADC input. Overrun error detection / protection is controlled by the ADDAT register.
13 - A/D CONVERTER ST10F269 Table 27 : ADC Sample Clock and Conversion Clock (TQFP144 devices) ADCON 15/14 ADCTC Conversion Clock tCC TCL1 = 1/2 x fXTAL At fCPU = 32MHz 00 TCL x 24 0.375µs 01 Reserved, do not use 10 11 Sample Clock tSC tSC = At fCPU = 32MHz 00 tCC 0.375µs 2 Reserved 01 tCC x 2 0.75µs 2 TCL x 96 1.5 µs 10 tCC x 4 1.50µs 2 TCL x 48 0.75 µs 11 tCC x 8 3.00µs 2 Notes: 1. Section 21.4.5 -: Direct Drive for TCL definition. 2.
ST10F269 14 - SERIAL CHANNELS 14 - SERIAL CHANNELS – – – – – – – – – Serial communication with other microcontrollers, microprocessors, terminals or external peripheral components is provided by two serial interfaces: the asynchronous / synchronous serial channel (ASCO) and the high-speed synchronous serial channel (SSC). Two dedicated Baud rate generators set up all standard Baud rates without the requirement of oscillator tuning.
14 - SERIAL CHANNELS ST10F269 Asynchronous Mode Baud rates fCPU For asynchronous operation, the Baud rate generator provides a clock with 16 times the rate of the established Baud rate. Every received bit is sampled at the 7th, 8th and 9th cycle of this clock.
ST10F269 14 - SERIAL CHANNELS Table 29 : Commonly Used Baud Rates by Reload Value and Deviation Errors (TQFP144 devices) S0BRS = ‘0’, fCPU = 32MHz S0BRS = ‘1’, fCPU = 32MHz Baud Rate (Baud) Deviation Error Reload Value Baud Rate (Baud) Deviation Error Reload Value 1000 000 ±0.0% 0000h 666 667 ±0.0% 0000h 56000 +5.0% / -0.8% 0010h / 001h 56000 +8.2% / -0.8% 000Ah / 000Bh 38400 +0.2% / -3.5% 0019h / 0020h 38400 +2.1% / -3.5% 0010h / 0011h 19200 +0.2% / -1.
14 - SERIAL CHANNELS ST10F269 14.1.2 - ASCO in Synchronous Mode In synchronous mode, data are transmitted or received synchronously to a shift clock which is generated by the ST10F269. Half-duplex communication up to 5M Baud (at 40MHz fCPU) or 4M Baud (at 32MHz) is possible in this mode.
ST10F269 14 - SERIAL CHANNELS Synchronous Mode Baud Rates For synchronous operation, the Baud rate generator provides a clock with 4 times the rate of the established Baud rate. The Baud rate for synchronous operation of serial channel ASC0 can be determined by the following formula: (S0BRL) represents the content of the reload register, taken as unsigned 13-bit integers, (S0BRS) represents the value of bit S0BRS (‘0’ or ‘1’), taken as integer.
14 - SERIAL CHANNELS ST10F269 Table 31 : Commonly Used Baud Rates by Reload Value and Deviation Errors (TQFP144 devices) S0BRS = ‘0’, fCPU = 32MHz S0BRS = ‘1’, fCPU = 32MHz Baud Rate (Baud) Deviation Error Reload Value Baud Rate (Baud) Deviation Error Reload Value 4 000 000 ±0.0% 0000h 2 666 667 ±0.0% 0000h 224 000 +5.0% / -0.8% 0011h / 0012h 224 000 +8.2% / -0.8% 000Bh / 000Ch 112 000 +2.0% / -0.8% 0023h / 0024h 112 000 +3.5% / -0.8% 0017h / 0018h 56 000 +0.6% / -0.
ST10F269 14 - SERIAL CHANNELS 14.2 - High Speed Synchronous Serial Channel (SSC) The High-Speed Synchronous Serial Interface SSC provides flexible high-speed serial communication between the ST10F269 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication. The serial clock signal can be generated by the SSC itself (master mode) or be received from an external master (slave mode).
14 - SERIAL CHANNELS ST10F269 Baud Rate Generation . The Baud rate generator is clocked by fCPU/2. The timer is counting downwards and can be started or stopped through the global enable bit SSCEN in register SSCCON. Register SSCBR is the dual-function Baud Rate Generator/Reload register. Reading SSCBR, while the SSC is enabled, returns the content of the timer. Reading SSCBR, while the SSC is disabled, returns the programmed reload value. In this mode the desired reload value can be written to SSCBR.
ST10F269 15 - CAN MODULES 15 - CAN MODULES The two integrated CAN modules (CAN1 and CAN2) are identical and handle the completely autonomous transmission and reception of CAN frames according to the CAN specification V2.0 part B (active). Each on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. These two CAN modules are both identical to the CAN module of the ST10F167.
15 - CAN MODULES ST10F269 The ST10F269 also supports single CAN Bus multiple (dual) interfaces using the open drain option of the CANx_TxD output as shown in Figure 48. Thanks to the OR-Wired Connection, only one transceiver is required. In this case the design of the application must take in account the wire length and the noise environment. Figure 48 : Single CAN Bus, Dual Interfaces, Single Transceiver CAN2 RxD TxD CAN1 RxD TxD * * +5V 2.
ST10F269 16 - REAL TIME CLOCK 16 - REAL TIME CLOCK The Real Time Clock is an independent timer, which clock is directly derived from the clock oscillator on XTAL1 input so that it can keep on running even in Idle or Power down mode (if enabled to). Registers access is implemented onto the XBUS.
16 - REAL TIME CLOCK ST10F269 Figure 51 : RTC Block Diagram Clock Oscillator RTCAI RTCSI RTCCON AlarmIT Basic Clock IT Programmable ALARM Register RTCAH Programmable PRESCALER Register RTCAL RTCPH RTCPL Reload = RTCH RTCDH RTCL 32 bit COUNTER RTCDL /64 20 bit DIVIDER be switch off. The RTC has 2 interrupt sources, one is triggered every basic clock period, the other one is the alarm. 16.1 - RTC registers 16.1.
ST10F269 16 - REAL TIME CLOCK mode. 2. All the bit of RTCCON are active high.
16 - REAL TIME CLOCK ST10F269 RTCPL. In order to keep the system clock, those registers are not reset. 16.1.2 - RTCPH & RTCPL: RTC PRESCALER Registers The 20-bit programmable prescaler divider is loaded with 2 registers. The 4 most significant bit are stored into RTCPH and the 16 Less significant bit are stored in RTCPL (EC06h) 15 14 They are write protected by bit RTOFF of RTCCON register, write operation is allowed if RTOFF is set.
ST10F269 16 - REAL TIME CLOCK When RTCD increments to reach 00000h, The 20-bit word stored into RTCPH, RTCPL registers is loaded in RTCD. Figure 53 : DIVIDER Counters 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTCDL RTCDH 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 20 bit word internal value of the Prescaler divider The only way to force their value is to write them via the XBUS. Those counters are write protected as well.
16 - REAL TIME CLOCK ST10F269 16.1.5 - RTCAH & RTCAL: RTC ALARM Registers When the programmable counters reach the 32-bit value stored into RTCAH & RTCAL registers, an alarm is triggered and the interrupt request RTAIR is generated. Those registers are not protected.
ST10F269 16 - REAL TIME CLOCK Interrupt control registers are common with CAPCOM1 Unit: CC10IC (RTCSI) and CC11IC (RTCAI).
17 - WATCHDOG TIMER ST10F269 17 - WATCHDOG TIMER due to hardware or software related failures, the software fails to do so, the watchdog timer overflows and generates an internal hardware reset. It pulls the RSTOUT pin low in order to allow external hardware components to be reset. Each of the different reset sources is indicated in the WDTCON register. The indicated bits are cleared with the EINIT instruction. The origin of the reset can be identified during the initialization phase.
ST10F269 17 - WATCHDOG TIMER The PONR flag of WDTCON register is set if the output voltage of the internal 3.3V supply falls below the threshold (typically 2V) of the power-on detection circuit. This circuit is efficient to detect major failures of the external 5V supply but if the internal 3.3V supply does not drop under 2 volts, the PONR flag is not set. This could be the case on fast switch-off / switch-on of the 5V supply.
18 - SYSTEM RESET ST10F269 18 - SYSTEM RESET System reset initializes the MCU in a predefined state. There are five ways to activate a reset state. The system start-up configuration is different for each case as shown in Table 37.
ST10F269 18 - SYSTEM RESET Figure 55 : Asynchronous Reset Sequence Internal Fetch 1 2 3 CPU Clock 6 or 8 TCL 1) RSTIN Asynchronous Reset Condition Flash under reset for internal charge pump ramping up 2.5µs max.
18 - SYSTEM RESET ST10F269 low. The reset is processed as an asynchronous reset. Figure 56 : Synchronous Reset Sequence External Fetch (RSTIN pulse > 1040 TCL) 4 TCL min. 12 TCL max. 6 or 8 TCL1) 1 2 3 4 5 6 7 8 9 CPU Clock 1024 TCL Internally pulled low RSTIN 2) RPD 200µA Discharge RSTOUT If VRPD > 2.5V Asynchronous 3) Reset is not entered.
ST10F269 18 - SYSTEM RESET Note maximum of 1038 TCL (4 TCL + 10 TCL + 1024 TCL). The system configuration is latched from PORT0 after a duration of 8 TCL / 4 CPU clocks (6 TCL / 3 CPU clocks if PLL is bypassed) and in case of external fetch, ALE, RD and R/W pins are driven to their inactive level. Program execution starts from memory location 00'0000h in code segment 0. This starting location will typically point to the general initialization routine.
18 - SYSTEM RESET programmed wait states. When READY is sampled inactive (high) after the programmed wait states the running external bus cycle is aborted. Then the internal reset sequence (1024 TCL) is started. The microcontroller behaviour is the same as for a short hardware reset, except that only P0.12...P0.6 bits are latched, while previously latched values of P0.5...P0.2 are cleared. 18.5 - RSTOUT, RSTIN, Bidirectional Reset 18.5.
ST10F269 18 - SYSTEM RESET Depending on the delay of the next applied reset, the MCU can enter a synchronous reset or an asynchronous reset. If RPD pin is below 2.5V an asynchronous reset starts, if RPD pin is above 2.5V a synchronous reset starts. (See Section 18.1 - and Section 18.2 -). Note that an internal pull-down is connected to RPD pin and can drive a 100µA to 200µA current. This Pull-down is turned on when RSTIN pin is low.
18 - SYSTEM RESET ST10F269 Figure 59 : Minimum External Reset Circuitry VDD RSTIN RPD + External Hardware RSTOUT ST10F269 R0 + b) a) a) Manual hardware reset1 b) For automatic power-up and interruptible power-down mode C1 C0 Figure 60 : External Reset Hardware Circuitry VDD VDD VDD External Hardware RSTIN RSTOUT R0 R2 ST10F269 D1 R1 D2 RPD + + C0 C1 Open - drain External Inverter Reset Source Table 38 : PORT0 Latched Configuration for the Different Resets P0H.5 P0H.
ST10F269 18 - SYSTEM RESET 3. Indirectly depend on PORT0. 4. Bits set if EA pin is 1.
19 - POWER REDUCTION MODES ST10F269 19 - POWER REDUCTION MODES Two different power reduction modes with different levels of power reduction have been implemented in the ST10F269. In Idle mode only CPU is stopped, while peripheral still operate. In Power Down mode both CPU and peripherals are stopped. Both mode are software activated by a protected instruction and are terminated in different ways as described in the following sections.
ST10F269 19 - POWER REDUCTION MODES EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0) 0 1: Interrupt on positive edge (rising) Enter Power Down mode if EXiIN = ‘0’, exit if EXxIN = ‘1’ (referred as ‘high’ active level) 1 0: Interrupt on negative edge (falling) Enter Power Down mode if EXiIN = ‘1’, exit if EXxIN = ‘0’ (referred as ‘low’ active level) 1 1: Interrupt on any edge (rising or falling) Always enter Power Down mode, exit if EXxIN level changed.
19 - POWER REDUCTION MODES ST10F269 Figure 62 : Simplified Powerdown Exit Circuitry VDD D Q Q1 cdQ enter PowerDown stop pll stop oscillator VDD Pull-up RPD Weak Pull-down (~ 200µA) external interrupt reset VDD CPU and Peripherals clocks D Q Q2 cdQ System clock Figure 63 : Powerdown Exit Sequence When Using an External Interrupt (PLL x 2) XTAL1 CPU clk Internal Powerdown signal External Interrupt RPD ExitPwrd (internal) ~ 2.
ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW 20 - SPECIAL FUNCTION REGISTER OVERVIEW The following table lists all SFRs which are implemented in the ST10F269 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. A SFR can be specified by its individual mnemonic name.
20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269 Table 40 : Special Function Registers Listed by Name (continued) Physical address Name CC9 CC9IC b CC10 CC10IC b CC11 CC11IC b CC12 CC12IC b CC13 CC13IC b CC14 CC14IC b CC15 CC15IC b CC16 CC16IC CC18 CC18IC CC19 CC19IC b b b b b b 126/184 4Bh CAPCOM Register 11 0000h FF8Eh C7h CAPCOM Register 11 Interrupt Control Register - - 00h FE98h 4Ch CAPCOM Register 12 0000h FF90h C8h CAPCOM Register 12 Interrupt Control Register - -
ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW Table 40 : Special Function Registers Listed by Name (continued) Physical address Name CC30 CC30IC 8-bit address FE7Ch b CC31 F18Ch Description Reset value 3Eh CAPCOM Register 30 0000h E C6h CAPCOM Register 30 Interrupt Control Register - - 00h 3Fh CAPCOM Register 31 0000h E CAh CAPCOM Register 31 Interrupt Control Register - - 00h FE7Eh CC31IC b F194h CCM0 b FF52h A9h CAPCOM Mode Control Register 0 0000h CCM1 b FF54h AAh
20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269 Table 40 : Special Function Registers Listed by Name (continued) Physical address Name MDL 8-bit address Description Reset value FE0Eh 07h CPU Multiply Divide Register – Low Word 0000h MRW b FFDAh EDh MAC Unit Repeat Word 0000h MSW b FFDEh EFh MAC Unit Status Word 0200h ODP2 b F1C2h E E1h Port 2 Open Drain Control Register 0000h ODP3 b F1C6h E E3h Port 3 Open Drain Control Register 0000h ODP4 b F1CAh E E5h Port 4 Open
ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW Table 40 : Special Function Registers Listed by Name (continued) Physical address Name 8-bit address Description Reset value PP0 F038h E 1Ch PWM Module Period Register 0 0000h PP1 F03Ah E 1Dh PWM Module Period Register 1 0000h PP2 F03Ch E 1Eh PWM Module Period Register 2 0000h PP3 F03Eh E 1Fh PWM Module Period Register 3 0000h 88h CPU Program Status Word 0000h PSW b FF10h PT0 F030h E 18h PWM Module Up/Down Counter 0 0
20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269 Table 40 : Special Function Registers Listed by Name (continued) Physical address Name T0IC b T0REL T1 T1IC b T1REL T2 T2CON b T2IC b T3 8-bit address Description Reset value FF9Ch CEh CAPCOM Timer 0 Interrupt Control Register - - 00h FE54h 2Ah CAPCOM Timer 0 Reload Register 0000h FE52h 29h CAPCOM Timer 1 Register 0000h FF9Eh CFh CAPCOM Timer 1 Interrupt Control Register - - 00h FE56h 2Bh CAPCOM Timer 1 Reload Register 0000h
ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW 20.1 - Identification Registers The ST10F269 has four Identification registers, mapped in ESFR space. These registers contain: Note: 256K and 128K versions of ST10F269 have the same IDMEM corresponding to 256K. – A manufacturer identifier, Both versions are based on the same device with the only difference that the two upper banks of Flash are not tested on 128K versions.
20 - SPECIAL FUNCTION REGISTER OVERVIEW ST10F269 20.2 - System Configuration Registers The ST10F269 has registers used for different configuration of the overall system. These registers are described below. SYSCON (FF12h / 89h) 15 14 13 STKSZ RW 12 11 SFR 10 9 8 7 Reset Value: 0xx0h 6 ROMS1 SGTDIS ROMEN BYTDIS CLKEN WRCFG CSCFG RW RW RW1 RW1 RW RW1 RW 5 4 3 PWD CFG OWD DIS BDR STEN RW RW RW 2 1 XPEN VISIBLE RW RW 0 XPERSHARE RW Notes: 1.
ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW ‘0’: Pins WR and BHE retain their normal function ‘1’: Pin WR acts as WRL, pin BHE acts as WRH. CLKEN System Clock Output Enable (CLKOUT) ‘0’: CLKOUT disabled: pin may be used for general purpose I/O ‘1’: CLKOUT enabled: pin outputs the system clock signal. Disable/Enable Control for Pin BHE (Set according to data bus width) BYTDIS ‘0’: Pin BHE enabled ‘1’: Pin BHE disabled, pin may be used for general purpose I/O.
20 - SPECIAL FUNCTION REGISTER OVERVIEW BUSCON4 (FF1Ah / 8Dh) 15 CSWEN4 RW 14 13 SFR 12 CSREN4 RDYPOL4 RDYEN4 RW RW ST10F269 Reset Value: 0000h 11 10 9 8 7 - BUSACT4 ALECTL4 - BTYP RW RW RW 6 5 4 MTTC4 RWDC4 RW RW 3 2 1 0 MCTC RW RW Notes: 1. BTYP (bit 6 and 7) are set according to the configuration of the bit l6 and l7 of PORT0 latched at the end of the reset sequence. 2. BUSCON0 is initialized with 0000h, if EA pin is high during reset.
ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW RP0H (F108h / 84h) ESFR 15 14 13 12 11 10 9 8 - - - - - - - - 7 Reset Value: --XXH 6 5 4 3 2 1 0 CLKSEL SALSEL CSSEL WRC R1-2 R2 R2 R2 Write Configuration Control WRC 2 ‘0’: Pin WR acts as WRL, pin BHE acts as WRH ‘1’: Pins WR and BHE retain their normal function CSSEL 2 Chip Select Line Selection (Number of active CS outputs) 0 0: 3 CS lines: CS2...CS0 0 1: 2 CS lines: CS1...
20 - SPECIAL FUNCTION REGISTER OVERVIEW EXICON (F1C0h / E0h 15 14 13 12 ST10F269 ESFR 11 10 9 8 Reset Value: 0000h 7 6 5 4 3 2 1 0 EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXI1ES EXI0ES RW RW RW RW RW RW RW RW EXIxES(x=7...0) External Interrupt x Edge Selection Field (x=7...0) 0 0: Fast external interrupts disabled: standard mode EXxIN pin not taken in account for entering/exiting Power Down mode.
ST10F269 20 - SPECIAL FUNCTION REGISTER OVERVIEW xxIC (yyyyh / zzh) SFR Area Reset Value: --00h 15 14 13 12 11 10 9 8 7 6 - - - - - - - - xxIR xxIE ILVL GLVL RW RW RW RW Bit 5 4 3 2 1 0 Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority. 3: Highest group priority 0: Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests.
20 - SPECIAL FUNCTION REGISTER OVERVIEW ’1’: The on-chip Real Time Clock is enabled and can be accessed. When both CAN are disabled via XPERCON setting, then any access in the address range 00’EE00h - 00’EFFFh will be directed to external memory interface, using the BUSCONx register corresponding to address matching ADDRSELx register. P4.4 and P4.7 can be used as General Purpose I/O when CAN2 is not enabled, and P4.5 and P4.6 can be used as General Purpose I/O when CAN1 is not enabled.
ST10F269 21 - ELECTRICAL CHARACTERISTICS 21 - ELECTRICAL CHARACTERISTICS 21.1 - Absolute Maximum Ratings Symbol Parameter Value Unit -0.5, +6.5 V VDD Voltage on VDD pins with respect to ground1 VIO Voltage on any pin with respect to ground1 -0.5, (VDD +0.5) V Voltage on VAREF pin with respect to ground1 -0.3, (VDD +0.3) V -10, +10 mA |100| mA 1.
21 - ELECTRICAL CHARACTERISTICS Symbol ST10F269 Parameter Test Conditions Min. Max. Unit VOL1 CC Output low voltage (all other outputs) 1 IOL1 = 1.6mA – 0.45 V VOH Output high voltage (PORT0, PORT1, Port4, 1 CC ALE, RD, WR, BHE, CLKOUT, RSTOUT) IOH = -500µA IOH = -2.4mA 0.9 VDD 2.4 – – V VOH1 CC Output high voltage (all other outputs) IOH = – 250µA IOH = – 1.6mA 0.9 VDD 2.
ST10F269 Symbol 21 - ELECTRICAL CHARACTERISTICS Parameter 10 IPD2 Power-down mode supply current (Real time clock enabled, oscillator enabled) 12 Test Conditions Min. Max. Unit VDD = 5.5V TA = 55°C fOSC = 25MHz – 2 + fOSC / 4 mA Notes: 1. ST10F269 pins are equipped with low-noise output drivers which significantly improve the device’s EMI performance. These low-noise drivers deliver their maximum current only until the respective target output level is reached.
21 - ELECTRICAL CHARACTERISTICS ST10F269 Figure 64 : Supply / Idle Current as a Function of Operating Frequency (PQFP144 devices) 120mA I [mA] ICCmax 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 I 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
ST10F269 21 - ELECTRICAL CHARACTERISTICS Figure 65 : Supply / Idle Current as a Function of Operating Frequency (TQFP144 devices) I [mA] ICCmax 100 93.
ST10F269 21.3.1 - A/D Converter Characteristics VDD = 5V ± 10%, VSS = 0V, TA = -40 to +85°C or -40 to +125°C, 4.0V ≤ VAREF ≤ VDD + 0.1V; VSS0.1V ≤ VAGND ≤ VSS + 0.2V Table 41 : A/D Converter Characteristics Limit Values Symbol Parameter Test Condition Unit minimum VAREF SR SR VAIN IAREF CC CC CAIN CC tS tC CC Analog Reference voltage maximum 4.0 VDD + 0.
ST10F269 21.3.2 - Conversion Timing Control When a conversion is started, first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage. The time to load the capacitances is referred to as the sample time ts. Next the sampled voltage is converted to a digital value in 10 successive steps, which correspond to the 10-bit resolution of the ADC.
ST10F269 Table 43 : ADC Sampling and Conversion Timing (TQFP144 devices) Sample Clock tSC Conversion Clock tCC ADCON.15/14 ADCTC TCL = 1/2 x fXTAL At fCPU = 32MHz ADCON.13/12 ADSTC tSC = At fCPU = 32MHz and ADCTC = 00 00 TCL x 24 0.375µs 00 tCC 0.375µs 01 Reserved, do not use Reserved 01 tCC x 2 0.75µs 10 TCL x 96 1.5 µs 10 tCC x 4 1.50µs 11 TCL x 48 0.75 µs 11 tCC x 8 3.00µs A complete conversion will take 14 tCC + 2 tSC + 4 TCL (fastest convertion rate = 6.06µs at 32MHz).
ST10F269 between two consecutive edges of the CPU clock, called “TCL”. The CPU clock signal can be generated by different mechanisms. The duration of TCL and its variation (and also the derived external timing) The mechanism used to generate the CPU clock P0.15-13 (P0H.7-5). depends on the mechanism used to generate fCPU. This influence must be regarded when calculating the timings for the ST10F269. The example for PLL operation shown in Figure 68 refers to a PLL factor of 4.
ST10F269 21.4.3 - Clock Generation Modes The Table 44 associates the combinations of these three bits with the respective clock generation mode. Table 44 : CPU Frequency Generation (PQFP144 devices) P0H.7 P0H.6 P0H.5 CPU Frequency fCPU = fXTAL x F External Clock Input Range1 1 1 1 fXTAL x 4 2.5 to 10MHz 1 1 0 fXTAL x 3 3.33 to 13.33MHz 1 0 1 fXTAL x 2 5 to 20MHz 1 0 0 fXTAL x 5 2 to 8MHz 0 1 1 fXTAL x 1 1 to 40MHz 0 1 0 fXTAL x 1.5 6.66 to 26.66MHz 0 0 1 fXTAL x 0.
ST10F269 21.4.4 - Prescaler Operation 21.4.6 - Oscillator Watchdog (OWD) When pins P0.15-13 (P0H.7-5) equal ’001’ during reset, the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fXTAL. An on-chip watchdog oscillator is implemented in the ST10F269.
ST10F269 The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes fCPU to keep it locked on fXTAL. The relative deviation of TCL is the maximum when it is referred to one TCL period. It decreases according to the formula and to the Figure 69 given below. For N periods of TCL the minimum value is computed using the corresponding deviation DN: TCL MIN D TCL = N D N × 1 – ------------- NOM 100 = where N = number of consecutive TCL periods and 1 ≤ N ≤ 40.
ST10F269 VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125 °C (TQFP144 devices) fCPU = fXTAL Parameter fCPU = fXTAL / 2 Symbol Minimum Maximum Minimum fCPU = fXTAL x F F = 1.5/2,/2.5/3/4/5 Unit Maximum Minimum Maximum Oscillator period tOSC SR 31.251 – 15.625 – 31.25 x N – ns High time t1 SR 12.52 – 6.252 – 12.52 – ns Low time t2 SR 12.52 – 6.252 – 12.52 – ns Rise time t3 SR – 3.1252 – 1.562 – 3.1252 ns Fall time t4 SR – 3.1252 – 1.562 – 3.1252 ns 1.
ST10F269 21.4.10 - Multiplexed Bus VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF, ALE cycle time = 6 TCL + 2tA + tC + tF (75ns at 40MHz CPU clock without wait states, PQFP144 devices). Symbol Max. CPU Clock = 40MHz Parameter Variable CPU Clock 1/2 TCL = 1 to 40MHz min. max. min. max. Unit Table 46 : Multiplexed Bus Characteristics (PQFP144 devices) t5 CC ALE high time 4 + tA – TCL - 8.5 + tA – ns t6 CC Address setup to ALE 2 + tA – TCL - 10.
ST10F269 Table 46 : Multiplexed Bus Characteristics (PQFP144 devices) Parameter Variable CPU Clock 1/2 TCL = 1 to 40MHz min. max. min. max. Unit Symbol Max. CPU Clock = 40MHz t42 CC ALE fall. edge to RdCS, WrCS (with RW delay) 7 + tA – TCL - 5.5+ tA – ns t43 CC ALE fall. edge to RdCS, WrCS (no RW delay) -5.5 + tA – -5.5 + tA – ns t44 CC Address float after RdCS, WrCS (with RW delay) – 0 – 0 ns 1 Address float after RdCS, WrCS (no RW delay) – 12.
Symbol Maximum CPU Clock = 32MHz Parameter Variable CPU Clock 1/2 TCL = 1 to 32MHz Unit ST10F269 Minimum Maximum Minimum Maximum -10 + tA – -10 + tA – ns – 6 – 6 ns – 21.625 – TCL + 6 ns t9 CC ALE falling edge to RD, WR (no RW-delay) t10 CC Address float after RD, WR (with RW-delay) 1 t11 CC Address float after RD, WR (no RW-delay) 1 t12 CC RD, WR low time (with RW-delay) 21.25 + tC – 2TCL - 10 + tC – ns t13 CC RD, WR low time (no RW-delay) 36.
ST10F269 Parameter Variable CPU Clock 1/2 TCL = 1 to 32MHz Unit Symbol Maximum CPU Clock = 32MHz Minimum Maximum Minimum Maximum – 0 – 0 ns – 15.625 – TCL ns t44 CC Address float after RdCS, WrCS (with RW delay) 1 t45 CC Address float after RdCS, WrCS (no RW delay) 1 t46 SR RdCS to Valid Data In (with RW delay) – 7.25 + tC – 2TCL - 24 + tC ns t47 SR RdCS to Valid Data In (no RW delay) – 22.875 + tC – 3TCL - 24 + tC ns t48 CC RdCS, WrCS Low Time (with RW delay) 21.
ST10F269 Figure 71 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Normal ALE CLKOUT t5 t25 t16 ALE t6 t38 t17 t40 t27 t39 CSx t6 t27 t17 A23-A16 (A15-A8) BHE Address t16 Read Cycle Address/Data Bus (P0) t6m t7 t18 Data In Address t10 t8 Address t19 t14 RD t13 t9 t11 t15 Write Cycle Address/Data Bus (P0) t12 t23 Data Out Address t8 WR WRL WRH 156/184 t22 t9 t12 t13
ST10F269 Figure 72 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Extended ALE CLKOUT t16 t5 t25 ALE t6 t38 t40 t17 t39 t27 CSx t6 t17 A23-A16 (A15-A8) BHE Address t27 Read Cycle Address/Data Bus (P0) t6 t7 Data In Address t8 t9 t18 t10 t19 t11 t14 RD t15 t12 t13 Write Cycle Address/Data Bus (P0) Address Data Out t23 t8 t9 WR WRL WRH t10 t11 t13 t22 t12 157/184
ST10F269 Figure 73 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Normal ALE, Read / Write Chip Select CLKOUT t5 t25 t16 ALE t6 t27 t17 A23-A16 (A15-A8) BHE Address t16 Read Cycle Address/Data Bus (P0) t6 t7 t51 Address Address Data In t44 t42 t52 t46 RdCSx t49 t43 t45 t47 Write Cycle Address/Data Bus (P0) t48 t56 Address Data Out t42 WrCSx t50 t43 t48 t49 158/184
ST10F269 Figure 74 : External Memory Cycle: Multiplexed Bus, With / Without Read / Write Delay, Extended ALE, Read / Write Chip Select CLKOUT t16 t5 t25 ALE t6 t17 A23-A16 (A15-A8) BHE Address t54 Read Cycle Address/Data Bus (P0) t6 t7 Data In Address t42 t43 t18 t44 t19 t45 t46 RdCSx t48 t47 t49 Write Cycle Address/Data Bus (P0) Address Data Out t42 t43 t56 t44 t45 t50 WrCSx t48 t49 159/184
ST10F269 21.4.11 - Demultiplexed Bus VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF, ALE cycle time = 4 TCL + 2tA + tC + tF (50ns at 40MHz CPU clock without wait states), PQFP144 devices. Symbol Maximum CPU Clock = 40MHz Parameter Variable CPU Clock 1/2 TCL = 1 to 40MHz Minimum Maximum Minimum Maximum Unit Table 48 : Demultiplexed Bus Characteristics (PQFP144 devices) t5 CC ALE high time 4 + tA – TCL - 8.5 + tA – ns t6 CC Address setup to ALE 2 + tA – TCL - 10.
ST10F269 Symbol Maximum CPU Clock = 40MHz Parameter Variable CPU Clock 1/2 TCL = 1 to 40MHz Minimum Maximum Minimum Maximum Unit Table 48 : Demultiplexed Bus Characteristics (PQFP144 devices) t41 CC Latched CS hold after RD, WR 2 + tF – TCL - 10.5 + tF – ns t82 CC Address setup to RdCS, WrCS (with RW-delay) 14.5 + 2tA – 2 TCL - 10.5 + 2tA – ns t83 CC Address setup to RdCS, WrCS (no RW-delay) 2 + 2tA – TCL - 10.
ST10F269 Symbol Parameter Maximum CPU Clock = 32MHz Variable CPU Clock 1/2 TCL = 1 to 32MHz Minimum Maximum Minimum Maximum Unit t81 CC Address/Unlatched CS setup to RD, WR (no RW-delay) 5.625 + 2tA – TCL -10 + 2tA – ns t12 CC RD, WR low time (with RW-delay) 21.25 + tC – 2TCL - 10 + tC – ns t13 CC RD, WR low time (no RW-delay) 36.875 + tC – 3TCL - 10 + tC – ns t14 SR RD to valid data in (with RW-delay) – 11.
ST10F269 Symbol Parameter Maximum CPU Clock = 32MHz Variable CPU Clock 1/2 TCL = 1 to 32MHz Minimum Maximum Minimum Maximum Unit t48 CC RdCS, WrCS Low Time (with RW-delay) 21.25 + tC – 2TCL - 10 + tC – ns t49 CC RdCS, WrCS Low Time (no RW-delay) 36.875 + tC – 3TCL - 10 + tC – ns t50 CC Data valid to WrCS 17.25 + tC – 2TCL - 14 + tC – ns t51 SR Data hold after RdCS 0 – 0 – ns t53 SR Data float after RdCS (with RW-delay) 3 – 21.
ST10F269 Figure 75 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE CLKOUT t5 t26 t16 ALE t6 t38 t41 t17 t41u 1) t39 CSx t6 A23-A16 A15-A0 (P1) BHE t28 (or t28h) t17 Address t18 Read Cycle Data Bus (P0) (D15-D8) D7-D0 Data In t80 t81 t20 t14 t21 t15 RD t12 t13 Write Cycle Data Bus (P0) (D15-D8) D7-D0 Data Out t80 t22 t81 WR WRL WRH t12 t13 Note: 1. Un-latched CSx = t41u = t41 TCL =10.5 + tF.
ST10F269 Figure 76 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Extended ALE CLKOUT t5 t26 t16 ALE t6 t38 t41 t17 t28 t39 CSx t6 t28 t17 A23-A16 A15-A0 (P1) BHE Address t18 Read Cycle Data Bus (P0) (D15-D8) D7-D0 Data In t20 t14 t80 t15 t81 t21 RD t12 t13 Write Cycle Data Bus (P0) (D15-D8) D7-D0 Data Out t80 t81 t22 WR WRL WRH t24 t12 t13 165/184
ST10F269 Figure 77 : External Memory Cycle: Demultiplexed Bus, With / Without Read / Write Delay, Normal ALE, Read / Write Chip Select CLKOUT t5 t26 t16 ALE t6 A23-A16 A15-A0 (P1) BHE t17 t55 Address t51 Read Cycle Data Bus (P0) (D15-D8) D7-D0 Data In t82 t83 t53 t46 t68 t47 RdCSx t48 t49 Write Cycle Data Bus (P0) (D15-D8) D7-D0 Data Out t82 t50 t83 WrCSx t48 t49 166/184 t57
ST10F269 Figure 78 : External Memory Cycle: Demultiplexed Bus, no Read / Write Delay, Extended ALE, Read / Write Chip Select CLKOUT t5 t26 t16 ALE t6 t55 t17 A23-A16 A15-A0 (P1) BHE Address t51 Read Cycle Data Bus (P0) (D15-D8) D7-D0 Data In t53 t46 t82 t47 t83 t68 RdCSx t48 t49 Write Cycle Data Bus (P0) (D15-D8) D7-D0 Data Out t82 t83 t50 t57 WrCSx t48 t49 167/184
ST10F269 21.4.12 - CLKOUT and READY VDD = 5V ± 10%, VSS = 0V, TA = -40 to + 125°C, CL = 50pF, PQFP144 devices Symbol Maximum CPU Clock = 40 MHz Parameter Variable CPU Clock 1/2TCL = 1 to 40 MHz Minimum Maximum Minimum Maximum Unit Table 50 : CLKOUT and READY Characteristics (PQFP144 devices) t29 CC CLKOUT cycle time 25 25 2TCL 2TCL ns t30 CC CLKOUT high time 4 – TCL – 8.5 – ns t31 CC CLKOUT low time 3 – TCL – 9.
ST10F269 VDD = 5V ± 10%, VSS = 0V, TA = -40 to + 125°C, CL = 50pF, TQFP144 devices Symbol Maximum CPU Clock = 32MHz Parameter Variable CPU Clock 1/2TCL = 1 to 32MHz Minimum Maximum Minimum Maximum Unit Table 51 : CLKOUT and READY Characteristics (TQFP144 devices) t29 CC CLKOUT cycle time 31.25 31.25 2TCL 2TCL ns t30 CC CLKOUT high time 9.625 – TCL – 6 – ns t31 CC CLKOUT low time 5.
ST10F269 Figure 79 : CLKOUT and READY READY wait state Running cycle 1) CLKOUT t32 MUX / Tri-state 6) t33 t30 t29 t31 t34 ALE 7) RD, WR 2) t35 Synchronous READY Asynchronous READY t36 t35 3) 3) t58 t59 3) t36 t58 t59 t60 4) 3) t37 5) 6) Notes: 1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS). 2. The leading edge of the respective command depends on RW-delay. 3.
ST10F269 Symbol Maximum CPU Clock = 40 MHz Parameter Variable CPU Clock 1/2TCL = 1 to 40 MHz Minimum Maximum Minimum Maximum Unit 21.4.13 - External Bus Arbitration VDD = 5V ± 10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF (PQFP144 devices) t61 SR HOLD input setup time to CLKOUT 15 – 15 – ns t62 CC CLKOUT to HLDA high or BREQ low delay – 12.5 – 12.5 ns t63 CC CLKOUT to HLDA low or BREQ high delay – 12.5 – 12.
ST10F269 . Figure 80 : External Bus Arbitration (Releasing the Bus) CLKOUT t61 HOLD t63 HLDA 1) t62 BREQ 2) t64 3) CSx (P6.x) 1) t66 Others Notes: 1. The ST10F269 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t64.
ST10F269 Figure 81 : External Bus Arbitration (Regaining the Bus) 2) CLKOUT t61 HOLD t62 HLDA t62 BREQ t62 t63 1) t65 CSx (On P6.x) t67 Other Signals Notes: 1. This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10F269 requesting the bus. 2. The next ST10F269 driven bus cycle may start here.
ST10F269 21.4.14 - High-Speed Synchronous Serial Interface (SSC) Timing 21.4.14.
ST10F269 Symbol t318 Maximum Baud rate=6.25MBd Variable Baud rate ( = 0001h) (=0001h-FFFFh) Symb ol Minimum Maximum Minimum Maximum Parameter SR Read data hold time after latch edge, phase error detection off (SSCPEN = 0) 41.25 – 2TCL + 10 t318 – Note: 1. Timing guaranteed by design.
ST10F269 Symbol Parameter Maximum Baud rate=10MBd ( = 0001h) Variable Baud rate (=0001h-FFFFh) Minimum Maximum Minimum Maximum Unit t317 SR Read data setup time before latch edge, phase error detection off (SSCPEN = 0) 6 – 6 – ns t318 SR Read data hold time after latch edge, phase error detection off (SSCPEN = 0) 31 – 2TCL + 6 – ns The formula for SSC Clock Cycle time is: t310 = 4 TCL * ( + 1) Where represents the content of the SSC Baud rate register, ta
ST10F269 Figure 83 : SSC Slave Timing 1) SCLK 00 00 00 00 t 00 00 00 t 00 315 MRST 00 t 00 00 t 0 0 t 00 311 314 315 1st Out Bit 317 MTSR 00 00 00 00 00 t 00 t310 00 00 00 00 t 0000 00 312 00 00 00 00 00 t 0 0 00t 0 313 2nd Out Bit 318 1st.In Bit 2) 2nd.In Bit 316 00 00 00 t 0 00 0 315 00 t 00 00 00 00 00 00 t 00 Last Out Bit 317 00 00 318 Last.In Bit Notes: 1. The phase and polarity of shift and latch edge of SCLK is programmable.
22 - PACKAGE MECHANICAL DATA ST10F269 22 - PACKAGE MECHANICAL DATA Figure 84 : Package Outline PQFP144 (28 x 28mm) A A2 A1 e 144 109 0,10 mm .004 inch SEATING PLANE 108 36 73 E3 E1 E B 1 c 72 L1 D3 D1 D L 37 K Millimeters 1 Inches (approx) Dimensions Minimum Typical A Maximum Minimum 4.07 A1 0.25 A2 3.17 B 0.22 c 0.13 D 30.95 D1 27.90 D3 Maximum 0.160 0.010 3.42 3.67 0.125 0.38 0.009 0.23 0.005 31.20 31.45 1.219 28.00 28.10 1.098 22.75 e 0.133 0.
ST10F269 22 - PACKAGE MECHANICAL DATA Figure 85 : Package Outline TQFP144 (20 x 20 x 1.40 mm) A A2 e 144 A1 109 108 36 73 E3 E1 E B 1 0,076 mm 0.03 inch SEATING PLANE c 72 L1 D3 D1 D L 37 K 0,25 mm .010 inch GAGE PLANE Millimeters 1 Inches (approx) Dimensions Minimum Typical A Maximum Minimum Typical 1.60 0.15 0.063 A1 0.05 A2 1.35 1.40 1.45 0.053 0.055 B 0.17 0.22 0.27 0.0067 0.0087 C 0.09 0.20 0.0035 0.002 0.006 D 22.00 0.866 20.00 0.787 D3 17.50 0.
23 - ORDERING INFORMATION ST10F269 23 - ORDERING INFORMATION Salestype Flash Program Memory (Bytes) Temperature range Package ST10F269Z2Q3 256K -40°C to +125°C PQFP144 (28 x 28 mm) ST10F269Z2Q6 256K -40°C to +85°C PQFP144 (28 x 28 mm) ST10F269Z2T3 256K -40°C to +125°C TQFP144 (20 x 20 x 1.40 mm) ST10F269Z2T6 256K -40°C to +85°C TQFP144 (20 x 20 x 1.
ERRATA SHEET ST10F269Zxxx-D LIMITATIONS AND CORRECTIONS 1 - DESCRIPTION This Errata sheet describes the functional and electrical problems known in the D revision of the ST10F269Zxxx. The revision number can be found in the third line on the ST10F269 package. It looks like: ’xxxxxxxxx D’ where "D" identifies the revision number. 2 - FUNCTIONAL PROBLEMS The following malfunctions are known in this step: 2.1 - PWRDN.
2 - FUNCTIONAL PROBLEMS ST10F269 2.2 - MAC.9 - CoCMP Instruction Inverted Operands The ST10 Family Programming Manual describes the CoCMP instruction as: subtracts a 40-bit signed operand from th 40-bit accumulator content (acc - op2\op1), and updates the N, Z and C flags in the MSW register, leaving the accumulator unchanged. On the device the reverse operation (op2\op1 - acc) has been implemented in the Mac Unit.
ST10F269 3 - DEVIATIONS FROM DC/AC PRELIMINARY SPECIFICATION 2.4 - ST_PORT.3 - Bad Behavior of Hysteresis Function on Input Falling Edge In the following conditions, a slow falling edge on a ST10F269 input may generate multiple events : – A falling edge is occuring. – AND the falling edge has a transition time between Vih and Vil longer than the CPU clock period.
ST10F269 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice.