Datasheet

PM8903A Device description
Doc ID 024147 Rev 1 17/33
Caution: Do not connect together the synchronization pin of two master devices in order to avoid any
damage to the ICs.
When two PM8903As are synchronized together they act as follows:
● Master mode
The SYNCH pin is configured as clock output. The device provides, on the SYNCH pin,
its internal switching clock information with a 180 ° time shifting.
● Slave mode
The SYNCH pin is configured as clock input. The device uses the clock information
received on the SYNCH pin to synchronize its internal switching clock.
5.7 Pulse-skipping
The PM8903A implements an ST proprietary adaptive pulse-skipping algorithm which
requires no configuration by the user and is independent from application setup and
parasites.
The algorithm allows to strongly increase the overall system efficiency skipping some
switching cycles (so reducing the equivalent switching frequency of the converter) when the
load current is low.
In many applications, MLCCs (multi layer ceramic capacitors) are used as the input or
output filter, or both. MLCCs can produce audible noise if the switching frequency is in the
human hearing range. To avoid audible noise, the PM8903A pulse-skipping algorithm limits
the minimum equivalent switching frequency above the audio band.
Pulse-skipping mode is enabled connecting a resistor between the PSKIP/MS pin and
ground, and selects the resistor value according to
Ta bl e 7 .
5.8 Multifunction pin PSKIP/MS
With this pin it is possible to:
● Enable/disable the pulse-skipping management
● Assign to the IC master or slave status
● Select the switching frequency.
Connect a resistor (R
PM
) between the PSKIP/MS pin and GND in order to set the IC
functionality according to
Tabl e 7 .
Table 7. PSKIP/MS pin configuration
R
PM
Pulse-skipping Synch mode Switching frequency
0 Ω Disabled Slave 1.1 MHz
24 kΩ Enabled Slave 1.1 MHz
56 kΩ Disabled Slave 0.8 MHz
110 kΩ Disabled Master 1.0 MHz
180 kΩ Enabled Master 1.1 MHz
240 kΩ
(or pin floating)
Disabled Master 1.1 MHz