Datasheet

Design guidelines PM8834
14/20 DocID15086 Rev 3
Figure 6. Equivalent circuit for MOSFET driver
5.3 Layout guidelines
The first priority when placing components for these applications has to be reserved to the
power section, minimizing the length of each connection and loop as much as possible. To
minimize noise and voltage spikes (also EMI and losses) power connections must be part of
a power plane and must consist of wide and thick copper traces: the loop must be
minimized.
Traces between the driver and the MOSFETs should be short and wide to minimize the
inductance of the traces, thus minimizing ringing in the driving signals. Moreover, the
number of vias needs to be minimized in order to reduce the related parasitic effect.
Small signal components and connections to critical nodes of the application as well as
bypass capacitors for the device supply are also important. Locate the bypass capacitor
(V
CC
capacitors) close to the device with the shortest possible loop and use wide copper
traces to minimize parasitic inductance.
To improve heat dissipation, place a copper area under the IC. This copper area may be
connected with other layers (if available) through vias to improve the thermal conductivity.
Figure 7. Power dissipation for capacitive
load of 10 nF
Figure 8. Power dissipation for capacitive
load of 10 nF with 4.7 Ω gate resistor
$09
5*$7( 5,
&*
9&&
/6'5,9(5 026)(7
*1'
287[
5KL5OR
$09




















       
3
6:
>:@
6XSSO\9ROWDJH>9@
3RZHU'LVVLSDWLRQIRUFDSDFLWLYHORDGRIQ)
N+]
N+]
N+]
$09












       
3VZ>:@
6XSSO\9ROWDJH>9@
3RZHU'LVVLSDWLRQIRUFDSDFLWLYHORDGRIQ)
ZLWK2KP*DWHUHVLVWRU
N+]
N+]
N+]