Datasheet

Device description and operation PM8834

10/20 DocID15086 Rev 3

Figure 3. Timing diagram

4.1.2 Enable pins

The PM8834 features two independent enable signals, ENABLE_1 and ENABLE_2, to

control the operation of each low-side driver. Both enable pins are internally pulled up to

VCC with a typ. 100 kΩ resistance and are active high. In applications where ENABLE_1

and ENABLE_2 are not in use, it is strongly recommended to connect these pins to VCC

directly or with a pull-up resistor. ENABLE_1 and ENABLE_2 are compatible to CMOS/TTL

levels and can be directly pulled up to VCC. By default, because of the internal pull-up, both

drivers are enabled. It is possible to disable one or both low-side drivers, connecting the

corresponding enable signal to GND. The enable pins cannot be used as input driving pins,

but only as driver control pins; they are not designed and tested in terms of matched

propagation delay time and maximum operating frequency.

4.2 Output stage

The output stage of the PM8834 makes use of ST’s proprietary lateral DMOS. Both N-

DMOS and P-DMOS have been sized to exhibit high driving peak current as well as low ON-

resistance. Typical peak current is 4 A while output resistances are 1 Ω and 0.7 Ω for P-

DMOS and N-DMOS resistance respectively.The device features adaptive anti cross-

conduction protection. The PM8834 continuously monitors the status of the internal N-

DMOS and P-DMOS. During a PWM transition, before switching on the desired DMOS, the

device waits until the other DMOS is completely turned off. No static current will then flow

from VCC to GND. During VCC startup, the internal N-DMOS is kept in an OFF state: with

typical VCC rise time, with slope >2 V/ms, the OUT pins are maintained at low level under

any operating condition. For VCC startup with very smooth rising edge, with slope < 2 V/ms,

the OUT pins can track the VCC rising edge until the UVLO threshold is reached, but the

voltage reached is maintained under 1.5 V under any operating condition.

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