Datasheet

Application examples PM6641
42/47 Doc ID 13510 Rev 3
The default switching frequency has been selected (750 kHz) and the tracking discharge
has been enabled in agreement with DDR2 JEDEC specifications. No external resistor
dividers are required for these output voltage levels. The allowed inductor current ripple is
about 35% of the expected peak load.
The power and signal components have been selected in agreement with
Chapter 8 on
page 35
equations.
The following schematic and bill of materials (BOM) are for reference design.
Figure 35. Suggested schematic for DDR2 and chipset power supply
C26
0603-100p
C4 0805-10u
C16
0603-100n
C27
0603-100p
R20 0603-68k
TP6 AGND
1
C28
0603-100p
TP1 VTTREF
1
VIN
C18
0603-33n
VCC
C19
0603-22n
C7 1206 - 100u
TP4 PG_1S05
1
AVCC
TP12 VOUT_1S05
1
C2 0805-10u
R12
0603-47k
AVCC
TP14 VTT
1
C6 1206 - 100u
TP5 VCC
1
R11 0603-100k
C21
0603-22n
R17 0603-68k
C25
0603-100p
C11 1206-22u
12
TP13 GND
1
U1
PM6641_QFPN
AGND_1
1
SET_SWF
2
VOUT_1S8
3
CSNS
4
SGND_1S8_1
5
SGND_1S8_2
6
VSW_1S8_1
7
VSW_1S8_2
8
VIN_1S8_1
9
VIN_1S8_2
10
VFB_1S8
11
COMP_1S8
12
SS_1S8
13
SS_1S05
14
COMP_1S05
15
VFB_1S05
16
SGND_1S05_1
17
VSW_1S05_1
19
VSW_1S05_2
20
VIN_1S05_2
22
PG_1S05
23
PG_1S8
24
EN_VTT
36
EN_1S5
35
EN_1S05
34
VIN_1S5
33
VSW_1S5_2
32
VSW_1S5_1
31
SGND_1S5_2
30
SGND_1S5_1
29
VFB_1S5
28
COMP_1S5
27
SS_1S5
26
PG_1S5
25
SGND_1S05_2
18
VIN_1S05_1
21
VCC
48
VTT_FB
47
DSCG
46
VTTREF
45
LDO_IN
44
VTT
43
VTT_GND
42
AVCC
41
AGND_2
40
SET_PH1
39
AGND_3
38
EN_1S8
37
THER MAL
49
L2
2839-1u5
1 2
C23 0603-470p
L3
2839-1u
1 2
R19 0603-68k
C12 0805-10u
TP2
PG_1S8
1
TP7 VIN
1
C15 1206 - 100u
C22 0603-330p
C20 0603-22n
C1
0603-1u
L1
2839-1u0
1 2
R32 0603-join
AVCC
TP10 VOUT_1S5
1
TP3
PG_1S5
1
TP9 VOUT_1S8
1
R21 0603-68k
AVCC
R22 0603-68k
R13 0603-68k
C3 0805-10u
R23 0603-68k
AVCC
SW1 SW DIP-4
1 2 3 4 5
6 7 8
VIN
C24 0603-330p
AVCC
C9 1206 - 100u
R18 0603-68k
C10 1206 - 100u
R1 0603-3R3
VIN