Datasheet

PM6641 Device description
Doc ID 13510 Rev 3 25/47
In order to obtain the typical integrative loop transfer function the signal stage must
compensate for the power stage pole (due to the output capacitor and the load) and zero
(above the loop bandwidth if ceramic output capacitors are selected). The signal stage
transfer function is:
Equation 2
Where g
M
is the power stage transconductance, K
L
is a design parameter and α is the gain
due to the output resistor divider (0.8 V / Vout). The external compensation network (R
c
, C
c
and C
RO
) introduces:
● One zero, to compensate the power stage pole:
● One pole in order to delete the static output voltage error;
● One pole, if necessary, in order to compensate the high frequency zero due to the
output capacitor ESR:
The control loop gain is obtained by multiplying G(s) by H(s):
Equation 3
This model provides good results if the control loop cut-off frequency f
CO
is lower than about
fsw/10.
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
++
+
α=
1
C
C
RsCsC
1RsC
Kg)s(G
C
Ro
CRoC
CC
Lm
(
)
ESOOCC
RRCRC
+
=
ESOCRO
RCRC
=
(
)
(
)
()
O
OESO
ESO
C
Ro
CRoC
CC
LmLOOP
R
1RRsC
1RsC
1
C
C
RsCsC
1RsC
Kg)s(G
++
+
⋅
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
++
+
α=