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May 2009 Doc ID 13510 Rev 3 1/47

PM6641

Monolithic VR for chipset and DDR2/3 supply

for ultra-mobile PC (UMPC) applications

Features

■ 0.8 V ±1% internal voltage reference

■ 2.7 V to 5.5 V input voltage range

■ Fast response, constant frequency,

current mode control

■ Three independent, adjustable, out-of-phase

SMPS for DDR2/3 (VDDQ) and chipset supply

■ Low noise DDR2/3 reference (VTTREF)

■ ±2 Apk LDO for DDR2/3 termination (VTT)

with foldback

■ S0-S5 states compliant DDR2/3 section

■ Active soft-end for all outputs

■ Selectable tracking discharge for VDDQ

■ Separate Power Good signals

■ Pulse skipping at light load

■ Programmable current limit and soft-start for

all outputs

■ Latched OVP, UVP protection

■ Thermal protection

Applications

■ DDR2/3 memory and chipset supply

■ UMPC and portable equipment

■ Handheld and PDAs

Description

The PM6641 is a monolithic voltage regulator

module specifically designed to supply DDR2/3

memory and chipset in ultra-mobile PC and real

estate constrained portable systems.

It integrates three independent, adjustable,

constant frequency buck converters, a ±2 Apk low

drop-out (LDO) linear regulator and a

±15 mA low noise buffered reference.

Each regulator provides basic UV and OV

protections, programmable soft-start and current

limit and active soft-end.

Pulse-skipping technique is performed to increase

efficiency at very light load.

VFQFPN-48 7x7 mm

Table 1. Device summary

Order codes Package Packaging

PM6641

VFQFPN-48 7x7 (exposed pad)

Tray

PM6641TR Tape and reel

www.st.com

Summary of content (47 pages)

PAGE 1
PM6641 Monolithic VR for chipset and DDR2/3 supply for ultra-mobile PC (UMPC) applications Features ■ 0.8 V ±1% internal voltage reference ■ 2.7 V to 5.
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Contents PM6641 Contents 1 Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 2.1 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical data . . . . . . .
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PM6641 8 9 Contents 7.11.1 Output overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.11.2 Output under voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.11.3 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.11.4 Input under voltage lock-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Components selection . . . . . . . . . . . .
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Doc ID 13510 Rev 3 1.8V VCC PG_1S8 PG_1S8 3.3V AVCC PG_1S05 PM6641 3.3V PG_1S05 EN_1S8 (S5) VTTREF VTTREF AGND SS_1S8 CSNS COMP_1S8 SGND_1S8 VFB_1S8 VOUT_1S8 VSW_1S8 EN_1S05 LDOIN VIN_1S8 VTTGND COMP_1S05 5V VTT SET_PH1 3.3V VTTFB AGND EN_VTT (S3) SS_1S05 PG_1S5 EN_1S5 SS_1S5 COMP_1S5 SGND_1S5 VFB_1S5 VSW_1S5 VIN_1S5 1.05V 3.3V PG_1S5 1.5V Figure 1.
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PM6641 Pin settings 2 Pin settings 2.1 Connections EN_1S8 (S5) Pin connection (through top view) VCC VTTFB DSCG VTTREF LDOIN VTT VTTGND AVCC AGND SET_PH1 AGND Figure 2.
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Pin settings 2.2 PM6641 Pin description Table 2. 6/47 Pin functions n° Pin Function 1 AGND 2 SET_SWF Switching frequency setting input. See Chapter 7.8: Switching frequency selection on page 29 3 VOUT_1S8 VDDQ/2 divider input and discharge path for 1.8 V rail. 4 CSNS 5 SGND_1S8 Switcher power ground for 1.8 V rail. 6 SGND_1S8 Switcher power ground for 1.8 V rail. 7 VSW_1S8 Switch node for 1.8 V rail. 8 VSW_1S8 Switch node for 1.8 V rail. 9 VIN_1S8 Power supply input for 1.
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PM6641 Pin settings Table 2. Pin functions (continued) n° Pin Function 26 SS_1S5 27 COMP_1S5 28 VFB_1S5 29 SGND_1S5 Switcher power ground for 1.5 V rail. 30 SGND_1S5 Switcher power ground for 1.5 V rail. 31 VSW_1S5 Switch node for 1.5 V rail. 32 VSW_1S5 Switch node for 1.5 V rail. 33 VIN_1S5 Power supply input for 1.5 V rail. 34 EN_1S05 Enable input for 1.05 V rail. 35 EN_1S5 Enable input for 1.5 V rail. 36 EN_VTT Enable input for VTT rail. High in S0 system states.
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Electrical data PM6641 3 Electrical data 3.1 Maximum rating Table 3. Absolute maximum ratings (1) Symbol Parameter VVIN VIN_x to SGND_x VVCC VCC to AGND or SGND_x VAVCC AVCC to AGND or SGND_x VIN = VAVCC VVCC = VAVCC Value Unit -0.3 to 6 AGND to SGND_x -0.3 to 0.3 VTTGND to SGND_x V VSW_x to SGND_x VVSW -0.3 to 6 VSW_x to AGND CSNS, PG_x, EN_x, DSCG, COMP_x, VFB_x, SS_x, SET_SWF, SET_PH1, VOUT_1S8 to AGND VTT, VTTREF, VTTFB to AGND -0.3 to VAVCC + 0.
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PM6641 3.3 Electrical data Recommended operating conditions Table 5. Recommended operating conditions Values Symbol Parameter Unit Min Typ Max VAVCC AVCC voltage range 4.5 5.5 VVCC VCC IC supply voltage 4.5 VAVCC VIN_x input voltage range 2.
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Electrical characteristics 4 PM6641 Electrical characteristics TA = 0 °C to 85 °C, AVCC = 5 V, VCC = 5 V, VIN_x = 3.3 V and LDOIN connected to 1.8 V output if not otherwise specified (a). Table 6.
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PM6641 Table 6. Electrical characteristics Electrical characteristics (continued) Values Symbol Parameter Test condition Unit Min Typ Max Thermal shutdown TSHDN Thermal shutdown threshold 150 Thermal shutdown hysteresis 15 °C Switching node – chipset 1.5 V rail Minimum on-time 200 RDSon,HS High side PMOS Ron 150 220 RDSon,LS Low side NMOS Ron 100 160 tOnmin IINLEAK ns mΩ VIN_1S5 leakage current Peak current limit VAVCC = VVCC = +5 V, all EN_1S5 low VIN = +5 V 1 μA VIN = +3.
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Electrical characteristics Table 6. PM6641 Electrical characteristics (continued) Values Symbol Parameter Test condition Unit Min LS turn-on VFB_1SX threshold with internal divider VFB_S1X to OUT_X Typ Max 0.2 V LS turn-on VFB_1SX threshold with external divider VFB_S1X to external divider 0.16 Power management section – chipset 1.05 V rail 0.
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PM6641 Table 6.
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Typical operating characteristics PM6641 5 Typical operating characteristics Figure 3. VDDQ and VTT soft-start without load Figure 4. VDDQ and VTT soft-start with AVG load Figure 5. 1V5 soft-start without load Figure 6. 1V5 soft-start with load Figure 7. 1V05 soft-start without load Figure 8.
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PM6641 Figure 9. Typical operating characteristics VDDQ output ripple and phase @ AVG current Figure 10. VTT, VTTREF output ripple @ AVG current Figure 11. 1V5 output ripple and phase @ AVG current Figure 12. 1V05 output ripple and phase @ AVG current Figure 13. SW reg. efficiency @ VIN = 3.3 V, FSW = 600 kHz Figure 14. VDDQ (1.
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Typical operating characteristics PM6641 Figure 15. 1.5 V load regulation Figure 16. 1.05 V load regulation g 1,536 1,053 1,052 1,532 1,530 1V5 1,528 1,526 1,524 1,522 0,00 Output Voltage [V] Output voltage (V) 1,534 1,051 1,050 1V05 1,049 1,048 0,50 1,00 1,50 2,00 Load Current [ A] 2,50 1,047 0,00 0,50 1,00 1,50 2,00 2,50 3,00 3,50 Load Current [A] Figure 17. VDDQ (1.8 V) load transient: 0-AVG Figure 18. VTT load transient: -1 A +1 A Figure 19.
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PM6641 Typical operating characteristics Figure 21. VDDQ e VTT soft-end with DSCG = AVCC Figure 22. VDDQ e VTT soft-end with DSCG = AGND Figure 23. Current limit Figure 24. Soft-OV (1V05) Figure 25. Output OV (1V5) @ RCSNS = 1 MΩ Figure 26. Output UV (1V5) Note: All the above measures and screen captures are based on PM6641EVAL demonstration board. Refer to PM6641 demonstration kit for details.
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Block diagram 6 PM6641 Block diagram Figure 27. Functional and block diagram VCC + _ PG_1S8 VIN_1S8 VREF+10% + _ ANTI X COND VIMAX ASM VREF-10% ZERO CROSS & VALLEY C.L. 0.9V VTTREF 1.237V VSW_1S8 VREF = 0.8V VTTFB VIMIN LDOIN _ PEAK CURR. LIMIT HiZ SGND_1S8 VTT + + _ R EN NTD NTD R VIMAX VOUT_1S8 COMP_1S8 gm PULSE SKIP ?3 + VFB_1S8 + SET_PH1 _ VTTGND VREF 0.
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PM6641 7 Device description Device description The PM6641 is an integrated voltage regulator module designed to supply DDR2/3 memory and chipset I/O in real estate constrained portable equipment and ultra-mobile PCs. The device consists of three buck regulators (two for chipset supply and one for main DDR supply), a low drop-out (LDO) linear regulator capable of ±2 Apk (DDR termination voltage) and a low noise buffered reference (DDR input buffer reference).
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Device description 7.1 PM6641 Memory supply The DDR2/3 section of PM6641 is based on the VDDQ rail, the VTT termination rail and the VTTREF reference voltage buffer. The VDDQ rail is provided by a step-down switching regulator whose output voltage, by default, is set to 1.8 V, in order to be compliant with DDR2 JEDEC specs. The output voltage can also be adjusted using an external resistor divider.
PAGE 21
PM6641 Device description the loop voltage reference is increased linearly from zero up to 0.8V in a long time (up to a couple of milliseconds) (see Chapter 7.6: Outputs soft-start on page 28 for details). When the EN_1S8 pin goes low, the VDDQ rail output capacitor is discharged through internal discharge MOSFET and, at the end of the capacitor discharge, the low side power MOSFET is eventually closed (see Chapter 7.7: Outputs soft-end on page 29 for details).
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Device description 7.1.4 PM6641 S3 and S5 power management pins According to DDR2/3 memories supply requirements, the PM6641 can manage all S0 to S5 system states just connecting EN_VTT – EN_1S8 pins to their respective sleep-mode signals in the notebook’s motherboard: connect EN_1S8 to S5 and EN_VTT to S3. Keeping EN_VTT and EN_1S8 high, the S0 (full-on) state is decoded and the outputs are alive.
PAGE 23
PM6641 Device description current mode loop to avoid sub-harmonic instability with duty cycle greater than 50%, is internally implemented and no further external components are required. The chipset supply is able to source the following average and peak currents, assuming 1 A peak-to-peak inductor current ripple: Table 9. Chipset supply currents Chipset supply rail [V] Average current [A] Peak current [A] 1.5 1.5 3.0 1.05 2.1 4.
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Device description 7.3 PM6641 SW regulators control loop The PM6641 switching regulators are buck converters employing a constant frequency, peak current mode PWM control loop, as shown in the following figure: Figure 28. SW regulator control loop Power Stage IL RES VO RO CO a KL VC CRO gm RC VREF CC Signal Stage In the current mode constant frequency loop the power stage is represented by a controlled current generator feeding the power stage output capacitor and load.
PAGE 25
PM6641 Device description In order to obtain the typical integrative loop transfer function the signal stage must compensate for the power stage pole (due to the output capacitor and the load) and zero (above the loop bandwidth if ceramic output capacitors are selected).
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Device description 7.4 PM6641 SW regulators pulse skipping and PWM mode In order to enhance the light load efficiency each switching regulator enters the pulse skipping algorithm when the output current sourced is too low.
PAGE 27
PM6641 7.5 Device description Output voltage divider PM6641 switching regulators are adjustable voltage converters. If the feedback pin (VFB_1S8, VFB_1S5, VFB_1S05 respectively belonging to VDDQ (1.8 V), 1.5 V, 1.05 V rail) is directly tied to the rail output capacitor the internal divider with pre-fixed output voltage value is activated and the nominal output voltages are selected. If the feedback pin is connected to the output voltage divider central tap (as depicted in Figure 30) Figure 30.
PAGE 28
Device description 7.6 PM6641 Outputs soft-start The soft-start function of each switching regulator is achieved by ramping up the SS pin voltage with a constant slew rate dV/dt. When the switching section is enabled (EN high), the SS pin constant current charges the capacitor connected between SS and ground pins. The SS voltage is used as reference of the switching regulator and the output voltage of the converter follows the ramp of the SS voltage. When the SS pin voltage is higher than 0.
PAGE 29
PM6641 7.7 Device description Outputs soft-end When the switching regulator enable pin (EN_1S8 for the VDDQ section, EN_1S5 and EN_1S05 for chipset sections) goes down or when UV or thermal protections are detected, the switching regulator output capacitor is actively discharged through a dedicated discharge MOSFET of about 25 Ω typical resistance.
PAGE 30
Device description 7.9 PM6641 Phase management When all the three switching regulators high side MOSFETs are turned on simultaneously the input root mean square (RMS) current could rise up to very high values, increasing the system losses and inducing external components overheating. It’s possible to reduce the input overall RMS current by inserting one ceramic capacitor as close as possible to each switching regulator power supply input, reducing the impulsive input current path.
PAGE 31
PM6641 Device description The synchronous mode of operation provides the following total input current: Equation 8 ICIN,SYNC = ∫ (I 1 TSW L1 + IL 2 + IL 3 ) dt = 1 2 TSW TSW (3I)2 TON whereas by shifting the three regulator turn on pulses of 120 deg the resulting total input current is given by Equation 9 ICIN,DELAY = that is 1 TSW ∫ (I + IL 2 + IL 3 ) dt = 2 L1 TSW 1 TSW (I 2 ) + I2 + I2 TON 3 ≅ 1.73 times smaller than the one computed before.
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Device description PM6641 where VREF = 0.9V is the constant voltage forced by CSNS pin, RCSNS [Ω] is the resistor connected between CSNS and AGND, α is the coefficient that collects the MOS current sensing scaling factor and other design parameters and ICL is the peak current limit [A]. The following table resumes values for all the switching regulators. Table 11. Typical SW regulators values SW regulator α 1.8V 333x10e3 1.5V 222x10e3 1.
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PM6641 7.11 Device description Fault management PM6641 has been conceived to constantly monitor the rails output voltage.
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Device description 7.11.3 PM6641 Thermal shutdown If the device temperature exceeds 150 °C, a thermal protection is triggered. As a consequence, the output soft end takes place for all the outputs of the PM6641 (VDDQ rail (1.8 V), VTT, VTTREF, 1.5 V, 1.05 V) by closing the output discharge MOSFET (see Chapter 7.7: Outputs soft-end on page 29 section for details).
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PM6641 8 Components selection Components selection The PM6641 switching regulator sections are buck converters employing a constant frequency, current mode PWM current loop (see Chapter 7.3: SW regulators control loop on page 24 section for details). The duty-cycle of the buck converter is, in steady-state conditions, given by Equation 11 D= VOUT VIN The switching frequency directly affects two parameters: 8.1 ● Inductor size: greater frequencies mean smaller inductances.
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Components selection PM6641 Once the inductor value is determined, the inductor current ripple is then recalculated: Equation 13 ΔIL,MAX = VIN,MAX − VOUT fsw ⋅ L ⋅ VOUT VIN,MAX The next step is the computation of the maximum RMS inductor current: Equation 14 IL,RMS = (ILOAD,MAX ) 2 + (ΔIL,MAX ) 2 12 The inductor must have an RMS current greater than IL,RMS in order to assure thermal stability.
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PM6641 Components selection The losses due to the input capacitor are thus maximized when the duty-cycle is 0.5: Equation 18 Ploss = ESR Cin ⋅ I2 CinRMS,MAX = ESR Cin ⋅ (0.5 ⋅ ILOAD,MAX ) 2 The input capacitor should be selected with a RMS rated current higher than ICinRMS,MAX. Tantalum capacitors are good in term of low ESR and small size, but they occasionally can burn out if subjected to very high current during operation.
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Components selection PM6641 If ceramic capacitors are used, the output voltage ripple due to inductor current ripple is negligible. Then the inductance could be smaller, reducing the size of the choke. In this case it is important that output capacitor can adsorb the inductor energy without generating an overvoltage condition when the system changes from a full load to a no load condition.
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PM6641 Components selection From the definition of cross-over frequency, the value of the compensation resistor is derived: Equation 25 GLOOP ( j2πfCO ) = 1 ⇒ R C = 2πfCO C O (RES + R O ) g m K L αR O A good choice for the cross-over frequency is to assign fCO equal to fSW . 10 The fixed parameters gm = 300 μs and KL = 4.4 s are design parameters, whereas the feedback divider factor (α) is application dependant (see Chapter 7.3: SW regulators control loop on page 24 section for details).
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Components selection 8.5 PM6641 Layout guidelines Each signal is referred to AGND, the analog ground. In a typical 4-layers PCB one internal layer should be dedicated to this common ground. The IC thermal pad must be connected to AGND plane through multiple VIAs, in order to remove the IC heat and to obtain the best performance. Furthermore, each switching regulator has a dedicated power ground (SGND_1Sxx); all these SGNDs must be star-connected, in a single point, with AGND.
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PM6641 9 Application examples Application examples The following application examples are typical or customized applications. Each example has been tested and evaluated and the schematic and BOM are available for reference design. 9.1 UMPC DDR2 and chipset power supply Figure 34. System architecture for DDR2 and chipset power supply VDDQ 1.8V @ 2.5A 3.3V VTT (LDO) 0.9V @ 2A PM6641 1.5V @ 2.8A 1.05V @ 4A This application is conceived for real estate constrained portable equipment with DDR2 memory.
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1 TP9 VOUT_1S8 1 VCC C1 R1 0603-3R3 1 L1 2 AVCC C22 0603-330p R11 0603-100k VIN C6 1206 - 100u 0603-22n C19 C2 0805-10u C15 1206 - 100u 0603-100n 0603-22n C21 C24 0603-330p R13 0603-68k 0603-join R32 2839-1u0 49 1 2 3 4 5 6 7 8 9 10 11 12 C12 0805-10u 0603-33n C18 1 AVCC 1 C16 1 0603-1u AGND_1 SET_SWF VOUT_1S8 CSNS SGND_1S8_1 SGND_1S8_2 VSW_1S8_1 VSW_1S8_2 VIN_1S8_1 VIN_1S8_2 VFB_1S8 COMP_1S8 THERMAL 1 2 AVCC C11 1206-22u 48 47 46 45 44 43 42 41 40 39 38 37 U1 PM6641_Q
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PM6641 Application examples Table 13. BOM suggested components for DDR2 and chipset power supply Qty Component Description Package 1 C1 Ceramic, 10 V, X5R, 10% SMD 0603 4 C2, C3, C4, C12 Ceramic, 10 V, X5R, 10% SMD 0805 5 C6, C7, C9, C10, C15 Ceramic, 4 V, X5R, 20% 1 C11 1 MFR Value Standard 1 µF GRM21BR61A106KE19 Murata 10 µF SMD 1206 AMK316BJ107ML Taiyo Yuden 100 µF Ceramic, 6.
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Package mechanical data 10 PM6641 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 14. VFQFPN-48 (7x7x1.0 mm) package mechanical data mm Dim. Min. Typ. Max. 0.80 0.90 1.00 A1 0.02 0.05 A2 0.65 1.00 A3 0.25 A b 0.18 0.23 0.
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PM6641 Package mechanical data Figure 36. VFQFPN-48 (7x7x1.
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Revision history 11 PM6641 Revision history Table 15. 46/47 Document revision history Date Revision Changes 16-May-2007 1 Initial release 16-Jan-2008 2 Document status promoted from preliminary data to datasheet. Updated: Table 2 on page 6, Table 3 on page 8, Table 6 on page 10, Chapter 7: Device description on page 19, Added: Chapter 9: Application examples on page 41., Chapter 8.
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PM6641 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.