User's Manual
Table Of Contents
- 1 Features
- 2 Product marking
- 3 System requirements
- 4 Development toolchains
- 5 Demonstration software
- 6 Ordering information
- 7 Hardware layout and configuration
- 7.1 Nucleo-68 board
- Figure 2. Nucleo-68 hardware block diagram
- Figure 3. Nucleo-68 board (top view)
- Figure 4. Nucleo-68 board (bottom view)
- Figure 5. Nucleo-68 board mechanical drawing
- Figure 6. Nucleo-68 board schematics
- Figure 7. Nucleo-68 board schematics - RF part
- Figure 8. Nucleo-68 board schematics - Connectors
- Figure 9. Nucleo-68 board schematics - Power management
- Figure 10. Nucleo-68 board schematics - ST-Link/V2-1
- 7.2 USB dongle
- 7.3 Getting started
- 7.4 Embedded ST-LINK/V2-1
- 7.5 Power supply and selection
- 7.6 Programing/debugging when the power supply is not from USB ST-LINK (5V_ST_link)
- 7.7 OSC clock sources
- 7.8 Reset sources
- 7.9 Virtual COM port: LPUART/USART
- 7.10 LEDs
- 7.11 Push buttons
- 7.12 Current measurement
- 7.13 Jumper configuration
- 7.1 Nucleo-68 board
- 8 Connectors
- Appendix A Nucleo-68 and USB dongle MCU IO assignment
- 9 Federal Communications Commission (FCC) and Industry Canada (IC) compliance statements
- 10 Revision history
Hardware layout and configuration UM2435
24/48 UM2435 Rev 2
Moreover, the board embeds a level shifter, which allows the user to debug the firmware
even if the target (STM32WB55) is supplied by a low-level voltage (1.8 to 3.3 V). There is no
jumper on the USB dongle.
The default jumper configuration and the V
DD
= 1.8 V setting is done according to Table 3.
Table 4. Default jumper configuration
Jumper Definition Default position Comment
JP1 Power selection ON [7-8] 5 V from ST-LINK
JP2 I
DD
measurement ON V
DD
current measurement
JP3 I
DD
measurement ON MCU V
DD
current measurement
JP4 RF power ON Possibility of isolating RF power
JP5 Level shifter All ON, except [1-2] that is OFF Level shifter
JP6 VDD_IN_SMPS ON V
DD
SMPS