Datasheet

M95M01-DF M95M01-R Instructions
Doc ID 13264 Rev 11 21/45
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed Write cycle that takes t
W
to complete (as specified in AC tables under Section 9: DC
and AC parameters).
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle t
W
, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
also reset at the end of the Write cycle t
W
.
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
● The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in Table 2.
● The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W
), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in Table 6. When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the t
W
Write cycle.
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.
The protection features of the device are summarized in Table 6.
When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W
) input pin.
Table 6. Protection modes
W
signal
SRWD
bit
Mode
Write protection of the
Status Register
Memory content
Protected area
(1)
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2.
Unprotected area
(1)
10
Software-
protected
(SPM)
Status Register is
writable (if the WREN
instruction has set the
WEL bit).
The values in the BP1
and BP0 bits can be
changed.
Write-protected
Ready to accept
Write instructions
00
11
01
Hardware-
protected
(HPM)
Status Register is
Hardware write-
protected.
The values in the BP1
and BP0 bits cannot be
changed.
Write-protected
Ready to accept
Write instructions