Datasheet

Instructions M95M01-DF M95M01-R
20/45 Doc ID 13264 Rev 11
6.3.4 SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W
) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W
) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.
6.4 Write Status Register (WRSR)
The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S
) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S
)
driven high. Chip Select (S
) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 11.
Figure 11. Write Status Register (WRSR) sequence
Table 5. Status Register format
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB