M95M01-DF M95M01-R 1-Mbit serial SPI bus EEPROM Datasheet − production data Features ■ Compatible with the Serial Peripheral Interface (SPI) bus ■ Memory array – 1 Mb (128 Kbytes) of EEPROM – Page size: 256 bytes SO8 (MN) 150 mil width ■ Write – Byte Write within 5 ms – Page Write within 5 ms ■ Additional Write lockable page (Identification page) ■ Write Protect: quarter, half or whole memory array ■ High-speed clock: 16 MHz ■ Single supply voltage: – 1.8 V to 5.5 V for M95M01-R – 1.7 V to 5.
Contents M95M01-DF M95M01-R Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 3.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.
M95M01-DF M95M01-R 6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 Read from Memory Array (READ) . . .
List of tables M95M01-DF M95M01-R List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. 4/45 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M95M01-DF M95M01-R List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections (top view) . . . . . . . . . .
Description 1 M95M01-DF M95M01-R Description The M95M01 devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as 131072 x 8 bits, accessed through the SPI bus. The M95M01-R devices can operate with a supply range from 1.8 V up to 5.5 V, the M95M01-DF devices can operate with a supply range from 1.7 V up to 5.5 V. These devices are guaranteed over the -40 °C/+85 °C temperature range. The M95M01-DF offers an additional page, named the Identification Page (256 bytes).
M95M01-DF M95M01-R Figure 2. Description 8-pin package connections (top view) M95xxx S Q W 1 2 3 4 VSS 8 7 6 5 VCC HOLD C D AI01790D 1. See Section 10: Package mechanical data section for package dimensions, and how to identify pin 1. Figure 3.
Memory organization 2 M95M01-DF M95M01-R Memory organization The memory is organized as shown in the following figure. Figure 4.
M95M01-DF M95M01-R 3 Signal description Signal description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are described next. 3.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device.
Signal description 3.6 M95M01-DF M95M01-R Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all Write instructions. 3.7 VCC supply voltage VCC is the supply voltage. 3.8 VSS ground VSS is the reference for all signals, including the VCC supply voltage.
M95M01-DF M95M01-R 4 Connecting to the SPI bus Connecting to the SPI bus All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. All output data bytes are shifted out of the device, most significant bit first.
Connecting to the SPI bus 4.1 M95M01-DF M95M01-R SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two modes: ● CPOL=0, CPHA=0 ● CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C).
M95M01-DF M95M01-R Operating features 5 Operating features 5.1 Supply voltage (VCC) 5.1.1 Operating supply voltage VCC Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 9: DC and AC parameters).
Operating features 5.1.4 M95M01-DF M95M01-R Power-down During power-down (continuous decrease of the VCC supply voltage below the minimum VCC operating voltage defined under Operating conditions in Section 9: DC and AC parameters), the device must be: 5.2 ● deselected (Chip Select S should be allowed to follow the voltage applied on VCC), ● in Standby Power mode (there should not be any internal write cycle in progress).
M95M01-DF M95M01-R Operating features The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C) is already low. Figure 7 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. 5.4 Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.
Instructions 6 M95M01-DF M95M01-R Instructions Each instruction starts with a single-byte code, as summarized in Table 3. If an invalid instruction is sent (one not contained in Table 3), the device automatically deselects itself. Table 3.
M95M01-DF M95M01-R 6.1 Instructions Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven high.
Instructions 6.2 M95M01-DF M95M01-R Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high.
M95M01-DF M95M01-R 6.3 Instructions Read Status Register (RDSR) The Read Status Register (RDSR) instruction is used to read the Status Register. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 10. Figure 10.
Instructions 6.3.4 M95M01-DF M95M01-R SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal enable the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low).
M95M01-DF M95M01-R Instructions Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the selftimed Write cycle that takes tW to complete (as specified in AC tables under Section 9: DC and AC parameters). While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed Write cycle tW, and 0 when the Write cycle is complete.
Instructions M95M01-DF M95M01-R When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two cases should be considered, depending on the state of the Write Protect (W) input pin: ● If Write Protect (W) is driven high, it is possible to write to the Status Register (provided that the WEL bit has previously been set by a WREN instruction).
M95M01-DF M95M01-R Instructions When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The instruction is not accepted, and is not executed, if a Write cycle is currently in progress. Table 7.
Instructions M95M01-DF M95M01-R The instruction is not accepted, and is not executed, under the following conditions: Note: ● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before), ● if a Write cycle is already in progress, ● if the device has not been deselected, by driving high Chip Select (S), at a byte boundary (after the eighth bit, b0, of the last data byte that has been latched in), ● if the addressed page is in the region protected
M95M01-DF M95M01-R 6.6.1 Instructions Cycling with Error Correction Code (ECC) The ECC is an internal logic function which is transparent for the SPI communication protocol. The ECC logic is implemented on each group of four EEPROM bytes(c). Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved.
Instructions 6.7 M95M01-DF M95M01-R Read Identification Page (available only in M95M01-D devices) The Identification Page (256 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see Table 4). The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D).
M95M01-DF M95M01-R 6.8 Instructions Write Identification Page (available only in M95M01-D devices) The Identification Page (256 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see Table 4). The Chip Select signal (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in on Serial Data Input (D).
Instructions 6.9 M95M01-DF M95M01-R Read Lock Status (available only in M95M01-Ddevices) The Read Lock Status instruction (see Table 4) is used to check whether the Identification Page is locked or not in Read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data Input (D). Address bit A10 must be 1, all other address bits are Don't Care.
M95M01-DF M95M01-R 6.10 Instructions Lock ID (available only in M95M01-D devices) The Lock ID instruction permanently locks the Identification Page in read-only mode. Before this instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high.
Power-up and delivery state M95M01-DF M95M01-R 7 Power-up and delivery state 7.1 Power-up state After power-up, the device is in the following state: ● Standby power mode, ● deselected (after power-up, a falling edge is required on Chip Select (S) before any instructions can be started), ● not in the Hold condition, ● the Write Enable Latch (WEL) is reset to 0, ● Write In Progress (WIP) is reset to 0.
M95M01-DF M95M01-R 8 Maximum rating Maximum rating Stressing the device outside the ratings listed in Table 8 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 8. Absolute maximum ratings Symbol TSTG TLEAD Parameter Min.
DC and AC parameters 9 M95M01-DF M95M01-R DC and AC parameters This section summarizes the operating conditions and the DC/AC characteristics of the device. Table 9. Operating conditions (M95M01-R, device grade 6) Symbol VCC TA Table 10. Parameter Min. Max. Unit Supply voltage 1.8 5.5 V Ambient operating temperature –40 85 °C Min. Max. Unit Supply voltage 1.7 5.5 V Ambient operating temperature –40 85 °C Max.
M95M01-DF M95M01-R Table 12. DC and AC parameters Capacitance Symbol COUT CIN Test conditions(1) Parameter Max. Unit VOUT = 0 V 8 pF Input capacitance (D) VIN = 0 V 8 pF Input capacitance (other pins) VIN = 0 V 6 pF Output capacitance (Q) Min. 1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz. Table 13. Symbol Ncycle Cycling performance by groups of four bytes Parameter(1) Test conditions Write cycle endurance(2) Min. Max.
DC and AC parameters Table 15. DC characteristics Symbol Parameter M95M01-DF M95M01-R Test conditions Min Max Unit ILI Input leakage current VIN = VSS or VCC ±2 µA ILO Output leakage current S = VCC, VOUT = VSS or VCC ±2 µA C = 0.1 VCC/0.9 VCC at 2 MHz, VCC = 1.8 V(1), Q = open 1.5 mA C = 0.1 VCC/0.9 VCC at 5 MHz, VCC = 1.8 V(1), Q = open 2(2) mA C = 0.1 VCC/0.9 VCC at 5 MHz, VCC = 2.5 V, Q = open 4 mA C = 0.1 VCC/0.9 VCC at 10 MHz, VCC = 2.5 V, Q = open 2(2) C = 0.1 VCC/0.
M95M01-DF M95M01-R Table 16. DC and AC parameters AC characteristics Test conditions specified in Table 9, Table 10 and Table 11 Symbol Alt. Parameter VCC ≥ 1.7 V(1) VCC ≥ 1.8 V(2) VCC ≥ 2.5 V(3) VCC ≥ 4.5 V(1) Unit Min. Max. Min. Max. Min. Max. Min. Max. fSCK Clock frequency D.C. 2 D.C. 5 D.C. 10 D.C.
DC and AC parameters M95M01-DF M95M01-R Figure 20. Serial input timing tSHSL S tCHSL tCH tSLCH tCHSH tSHCH C tDVCH tCHCL tCL tCLCH tCHDX D Q LSB IN MSB IN High impedance AI01447d Figure 21.
M95M01-DF M95M01-R DC and AC parameters Figure 22.
Package mechanical data 10 M95M01-DF M95M01-R Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 23. SO8N – 8-lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 A c ccc b e 0.
M95M01-DF M95M01-R Package mechanical data Figure 24. TSSOP8 – 8-lead thin shrink small outline, package outline D 8 5 c E1 1 E 4 α A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 18. TSSOP8 – 8-lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ Min A Max Min 1.200 A1 0.050 0.150 0.800 1.050 b 0.190 c 0.090 A2 Typ 1.000 CP Max 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.
Package mechanical data M95M01-DF M95M01-R Figure 25. M95M01-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package outline bbb Z e2 D Y X e F Detail A E F e3 aaa Reference e1 A A2 (4X) Wafer back side G G Orientation Bumps side Side view Bump A1 eee Z b Øccc Øddd Seating plane M Z XY M Z Detail A Rotated 90 ° 1. Drawing is not to scale.
M95M01-DF M95M01-R Table 19. Package mechanical data M95M01-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.540 0.500 0.580 0.0213 0.0197 0.0228 A1 0.190 0.0075 A2 0.350 0.0138 b 0.270 0.0106 D 2.560 2.580 0.1008 0.1016 E 1.698 1.718 0.0669 0.0676 e 1.000 0.0394 e1 0.866 0.0341 e2 0.500 0.0197 e3 0.500 0.0197 F 0.416 0.0164 G 0.780 0.0307 8 8 aaa 0.110 0.0039 bbb 0.
Part numbering 11 M95M01-DF M95M01-R Part numbering Table 20. Ordering information scheme Example: Device type M95 = SPI serial access EEPROM M95M01 R MN 6 T P /K Device function M01- = 1 Mbit (131072 x 8) M01-D = 1 Mbit plus Identification page Operating voltage R = VCC = 1.8 to 5.5 V F = VCC = 1.7 to 5.5 V Package MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) CS = WLCSP Device grade 6 = Industrial temperature range, –40 to 85 °C.
M95M01-DF M95M01-R 12 Revision history Revision history Table 21. Document revision history Date Revision 13-Mar-2007 1 Initial release. 15-May-2007 2 VCC conditions modified in Table 15: AC characteristics (M95M01-R6, VCC < 2.5 V). Small text changes. 21-Jun-2007 3 The device endurance is specified at more than 1 000 000 (1 million) cycles (corrected on page 1). 4 Schmitt trigger inputs for enhanced noise margin added to Features on page 1.
Revision history Table 21. Date 44/45 M95M01-DF M95M01-R Document revision history (continued) Revision Changes 20-Jun-2012 9 Datasheet split into: – M95M01-125 datasheet for automotive products (range 3), – M95M01-DF, M95M01-R (this datasheet) for standard products (range 6).
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