Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsIntegrated Circuits (ICs)SO 8 64 kBit 8 K x 8

1/42May 2005

M95320 M95320-W M95320-R M95320-S

M95640 M95640-W M95640-R M95640-S

32Kbit and 64Kbit Serial SPI Bus EEPROMs

With High Speed Clock

FEATURES SUMMARY

■ Compatible with SPI Bus Serial Interface

(Positive Clock SPI Modes)

■ Single Supply Voltage:

– 4.5 to 5.5V for M95320 and M95640

– 2.5 to 5.5V for M95320-W and M95320-W

– 1.8 to 5.5V for M95320-R and M95640-R

– 1.65 to 5.5V for M95320-S and M95640-S

■ 20MHz, 10MHz, 5MHz or 2MHz clock rates

■ 5ms or 10ms Write Time

■ Status Register

■ Hardware Protection of the Status Register

■ BYTE and PAGE WRITE (up to 32 Bytes)

■ Self-Timed Programming Cycle

■ Adjustable Size Read-Only EEPROM Area

■ Enhanced ESD Protection

■ More than 100000 or 1 million Erase/Write

Cycles (depending on ordering options)

■ More than 40-Year Data Retention

Table 1. Product List

Figure 1. Packages

Reference Part Number

M95320

M95320-W

M95320-R

M95320-S

M95640

M95640-W

M95640-R

M95640-S

PDIP8 (BN)

0.25 mm frame

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

MLP8 (MB)

2x3 mm

Summary of content (42 pages)

PAGE 1
M95320 M95320-W M95320-R M95320-S M95640 M95640-W M95640-R M95640-S 32Kbit and 64Kbit Serial SPI Bus EEPROMs With High Speed Clock FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Compatible with SPI Bus Serial Interface (Positive Clock SPI Modes) Single Supply Voltage: – 4.5 to 5.5V for M95320 and M95640 – 2.5 to 5.5V for M95320-W and M95320-W – 1.8 to 5.5V for M95320-R and M95640-R – 1.65 to 5.
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M95640, M95320 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . .
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M95640, M95320 Figure 7. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 6. Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . .
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M95640, M95320 Table 22. AC Characteristics (M95320 and M95640, Device Grade 6). . . . . . . . . . . . . . . . . . . . . . 28 Table 23. AC Characteristics (M95320 and M95640, Device Grade 3). . . . . . . . . . . . . . . . . . . . . . 29 Table 24. AC Characteristics (M95320-W and M95640-W, Device Grade 6) . . . . . . . . . . . . . . . . . 30 Table 25. AC Characteristics (M95320-W and M95640-W, Device Grade 3) . . . . . . . . . . . . . . . . . 31 Table 26. AC Characteristics (M95320-R and M95640-R) . . . . .
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M95640, M95320 SUMMARY DESCRIPTION These electrically erasable programmable memory (EEPROM) devices are accessed by a high speed SPI-compatible bus. The M95320, M95320-W, M95320-R and M95320-S are 32Kbit devices organized as 4096 x 8 bits. The M95640, M95640-W, M95640-R and M95640-S are 64Kbit devices organized as 8192 x 8 bits. The device is accessed by a simple serial interface that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 3. and Figure 2..
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M95640, M95320 SIGNAL DESCRIPTION During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held High or Low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 16. to Table 20.). These signals are described next. Serial Data Output (Q). This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of Serial Clock (C). Serial Data Input (D).
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M95640, M95320 CONNECTING TO THE SPI BUS (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction (such as the Read from Memory Array and Read Status Register instructions) have been clocked into the device. Figure 4. shows three devices, connected to an MCU, on a SPI bus. Only one device is selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the others being high impedance. These devices are fully compatible with the SPI protocol.
PAGE 8
M95640, M95320 SPI Modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C). The difference between the two modes, as shown in Figure 5.
PAGE 9
M95640, M95320 OPERATING FEATURES Power-Up When the power supply is turned on, VCC rises from VSS to VCC. During this time, the Chip Select (S) must be allowed to follow the VCC voltage. It must not be allowed to float, but should be connected to VCC via a suitable pull-up resistor. As a built in safety feature, Chip Select (S) is edge sensitive as well as level sensitive. After Powerup, the device does not become selected until a falling edge has first been detected on Chip Select (S).
PAGE 10
M95640, M95320 Figure 6. Hold Condition Activation C HOLD Hold Condition Hold Condition AI02029D Status Register Figure 7. shows the position of the Status Register in the control logic of the device. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status Register cycle. WEL bit.
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M95640, M95320 – The ‘last bit of the instruction’ can be the eighth bit of the instruction code, or the eighth bit of a data byte, depending on the instruction (except for Read Status Register (RDSR) and Read (READ) instructions). – The ‘next rising edge of Serial Clock (C)’ might (or might not) be the next bus transaction for some other device on the SPI bus. Table 5.
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M95640, M95320 MEMORY ORGANIZATION The memory is organized as shown in Figure 7.. Figure 7.
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M95640, M95320 INSTRUCTIONS Each instruction starts with a single-byte code, as summarized in Table 6.. If an invalid instruction is sent (one not contained in Table 6.), the device automatically deselects itself. Table 6.
PAGE 14
M95640, M95320 Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 8., to send this instruction to the device, Chip Select (S) is driven Low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven High. Figure 8.
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M95640, M95320 BP1, BP0 bits. The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 4.) becomes protected against Write (WRITE) instructions.
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M95640, M95320 Write Status Register (WRSR) The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).
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M95640, M95320 If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP1, BP0) bits of the Status Register, can be used. (BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
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M95640, M95320 When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a single READ instruction. The Read cycle is terminated by driving Chip Select (S) High. The rising edge of the Chip Select (S) signal can occur at any time during the cycle. The first byte addressed can be any byte within any page.
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M95640, M95320 Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these devices is 32 bytes).
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M95640, M95320 Figure 14. Page Write (WRITE) Sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D 3 2 Data Byte 1 1 0 7 6 5 4 3 2 0 1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data Byte 2 D 7 6 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 2 Data Byte N 1 0 6 5 4 3 2 1 0 AI01796D Note: Depending on the memory size, as shown in Table 8., the most significant address bits are Don’t Care.
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M95640, M95320 POWER-UP AND DELIVERY STATE Power-up State After Power-up, the device is in the following state: – Standby Power mode – deselected (after Power-up, a falling edge is required on Chip Select (S) before any instructions can be started). – not in the Hold Condition – the Write Enable Latch (WEL) is reset to 0 – Write In Progress (WIP) is reset to 0 The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous powerdown (they are non-volatile bits).
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M95640, M95320 MAXIMUM RATING Stressing the device outside the ratings listed in Table 9. may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 9.
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M95640, M95320 DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure- ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 10.
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M95640, M95320 Figure 15. AC Measurement I/O Waveform Input Levels Input and Output Timing Reference Levels 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI00825B Table 15. Capacitance Symbol COUT CIN Parameter Test Condition Max. Unit VOUT = 0V 8 pF Input Capacitance (D) VIN = 0V 8 pF Input Capacitance (other pins) VIN = 0V 6 pF Output Capacitance (Q) Min. Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 5MHz. Table 16.
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M95640, M95320 Table 17. DC Characteristics (M95320 and M95640, Device Grade 3) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICC Supply Current Supply Current (Standby) ICC1 Test Condition Min. Max. Unit VIN = VSS or VCC ±2 µA S = VCC, VOUT = VSS or VCC ±2 µA C = 0.1VCC/0.9VCC at 2MHz, VCC = 5V, Q = open, Previous Product 2 2 mA C = 0.1VCC/0.9VCC at 5MHz, VCC = 5V, Q = open, Current Product 3 4 mA C = 0.1VCC/0.
PAGE 26
M95640, M95320 Table 18. DC Characteristics (M95320-W and M95640-W, Device Grade 6) Symbol Parameter ILI Input Leakage Current ILO Output Leakage Current ICC Supply Current Supply Current (Standby) ICC1 Test Condition Min. Max. Unit VIN = VSS or VCC ±2 µA S = VCC, VOUT = VSS or VCC ±2 µA C = 0.1VCC/0.9VCC at 2MHz, VCC = 2.5V, Q = open, Previous Product 1 2 mA C = 0.1VCC/0.9VCC at 5MHz, VCC = 2.5V, Q = open, Current Product 2 3 mA C = 0.1VCC/0.9VCC at 10MHz, VCC = 2.
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M95640, M95320 Table 20. DC Characteristics (M95320-R and M95640-R) Symbol Parameter Max.1,2 Unit VIN = VSS or VCC ±1 µA S = VCC, VOUT = VSS or VCC ±1 µA C = 0.1VCC/0.9VCC at 5MHz, VCC = 1.8 V, Q = open 3 mA S = VCC, VIN = VSS or VCC, VCC = 1.8V 1 µA Test Condition Min.1,2 ILI Input Leakage Current ILO Output Leakage Current ICC Supply Current ICC1 Supply Current (Standby) VIL Input Low Voltage –0.45 0.3 VCC V VIH Input High Voltage 0.
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M95640, M95320 Table 22. AC Characteristics (M95320 and M95640, Device Grade 6) Test conditions specified in Table 14. and Table 10. Symbol fC Alt. fSCK Parameter Clock Frequency Previous Product Version 3 Current Product Version4 New Product Version5,6 Min. Max. Min. Max. Min. Max. D.C. 5 D.C. 10 D.C.
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M95640, M95320 Table 23. AC Characteristics (M95320 and M95640, Device Grade 3) Test conditions specified in Table 14. and Table 10. Symbol Alt. Parameter Previous Product Version 3 Current Product Version4 New Product Version5,6 Min. Max. Min. Max. Min. Max. 2 D.C. 5 D.C. 20 Unit fC fSCK Clock Frequency D.C.
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M95640, M95320 Table 24. AC Characteristics (M95320-W and M95640-W, Device Grade 6) Test conditions specified in Table 14. and Table 11. Symbol Alt. Parameter Previous Product Version 3 Current Product Version4 New Product Version5,6 Min. Max. Min. Max. Min. Max. 2 D.C. 5 D.C. 10 Unit fC fSCK Clock Frequency D.C.
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M95640, M95320 Table 25. AC Characteristics (M95320-W and M95640-W, Device Grade 3) Test conditions specified in Table 14. and Table 11. Symbol Alt. Parameter Current Product Version3 New Product Version4,5 Min. Max. Min. Max. D.C. 5 D.C.
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M95640, M95320 Table 26. AC Characteristics (M95320-R and M95640-R) Test conditions specified in Table 14. and Table 12. Max.3,4 Unit D.C. 5 MHz Alt. fC fSCK Clock Frequency tSLCH tCSS1 S Active Setup Time 60 ns tSHCH tCSS2 S Not Active Setup Time 60 ns tSHSL tCS S Deselect Time 90 ns tCHSH tCSH S Active Hold Time 60 ns S Not Active Hold Time 60 ns tCHSL Parameter Min.
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M95640, M95320 Table 27. AC Characteristics (M95320-S Device Grade 3) Test conditions specified in Table 14. and Table 12. Min.3,4 Max.3,4 Unit Clock Frequency D.C. 2 MHz tCSS1 S Active Setup Time 150 ns tSHCH tCSS2 S Not Active Setup Time 150 ns tSHSL tCS S Deselect Time 200 ns tCHSH tCSH S Active Hold Time 150 ns S Not Active Hold Time 150 ns Symbol Alt.
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M95640, M95320 Figure 16. Serial Input Timing tSHSL S tCHSL tSLCH tCHSH tSHCH C tDVCH tCHCL tCHDX tCLCH LSB IN MSB IN D Q High Impedance AI01447C Figure 17.
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M95640, M95320 Figure 18. Output Timing S tCH C tCLQV tCLQX tCLQV tCL tSHQZ tCLQX LSB OUT Q tQLQH tQHQL D ADDR.
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M95640, M95320 PACKAGE MECHANICAL Figure 19. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline E b2 A2 A1 b A L c e eA eB D 8 E1 1 PDIP-B Note: Drawing is not to scale. Table 28. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data mm inches Symb. Typ. Min. A Typ. Min. 5.33 A1 Max. 0.210 0.38 0.015 A2 3.30 2.92 4.95 0.130 0.115 0.195 b 0.46 0.36 0.56 0.018 0.014 0.022 b2 1.52 1.14 1.78 0.060 0.045 0.070 c 0.25 0.20 0.36 0.010 0.
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M95640, M95320 Figure 20. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline h x 45˚ A C B CP e D N E H 1 A1 α L SO-a Note: Drawing is not to scale. Table 29. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data mm inches Symb. Typ. Min. Max. A 1.35 A1 Min. Max. 1.75 0.053 0.069 0.10 0.25 0.004 0.010 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.
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M95640, M95320 Figure 21. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline D 8 5 c E1 1 E 4 α L A1 A A2 L1 CP b e TSSOP8AM Note: Drawing is not to scale. Table 30. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data mm inches Symbol Typ. Min. A 0.050 0.150 0.800 1.050 b 0.190 c 0.090 A2 Typ. Min. 1.200 A1 1.000 CP Max. 0.0472 0.0020 0.0059 0.0315 0.0413 0.300 0.0075 0.0118 0.200 0.0035 0.0079 0.0394 0.100 0.0039 D 3.000 2.900 3.
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M95640, M95320 Figure 22. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, Package Outline e D b L1 L3 E E2 L A D2 ddd A1 UFDFPN-01 Note: Drawing is not to scale. Table 31. MLP8 - 8-lead Ultra thin Fine pitch Dual Flat No Lead, Package Mechanical Data millimeters inches Symbol A Typ Min Max Typ Min Max 0.55 0.50 0.60 0.022 0.020 0.024 0.00 0.05 0.000 0.002 0.20 0.30 0.008 0.012 0.061 0.065 A1 b 0.25 D 2.00 D2 0.079 1.55 ddd E 0.010 1.65 0.05 3.00 E2 0.002 0.
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M95640, M95320 PART NUMBERING Table 32. Ordering Information Scheme Example: M95640 – W MN 6 T P Device Type M95 = SPI serial access EEPROM Device Function2 640 = 64 Kbit (8192 x 8) 320 = 32 Kbit (4096 x 8) Operating Voltage blank = VCC = 4.5 to 5.5V W = VCC = 2.5 to 5.5V R = VCC = 1.8 to 5.5V S = VCC = 1.65 to 5.5V Package BN = PDIP8 MN = SO8 (150 mil width) DW = TSSOP8 (169 mil width) MB = MLP8 (2x3 mm) Device Grade 6 = Industrial temperature range, –40 to 85 °C.
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M95640, M95320 REVISION HISTORY Table 33. Document Revision History Date Rev. Description of Revision 13-Jul-2000 1.2 Human Body Model meets JEDEC std (Table 2). Minor adjustments on pp 1,11,15. New clause on p7. Addition of TSSOP8 package on pp 1, 2, Ordering Info, Mechanical Data 16-Mar-2001 1.3 Test condition added ILI and ILO, and specification of tDLDH and tDHDL removed. tCLCH, tCHCL, tDLDH and tDHDL changed to 50ns for the -V range. “-V” Voltage range changed to “2.7V to 3.6V” throughout.
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M95640, M95320 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice.