Datasheet

ManualsBrandsSTMICROELECTRONICS ManualsIntegrated Circuits (ICs)TSSOP 8 512 kBit 64 K x 8

This is information on a product in full production.

June 2013 DocID11124 Rev 21 1/50

M95512-W M95512-R

M95512-DR M95512-DF

512-Kbit serial SPI bus EEPROM

Datasheet - production data

Features

• Compatible with the Serial Peripheral Interface

(SPI) bus

• Memory array

– 512 Kb (64 Kbytes) of EEPROM

– Page size: 128 bytes

• Write

– Byte Write within 5 ms

– Page Write within 5 ms

• Additional Write lockable page (Identification

page)

• Write Protect: quarter, half or whole memory

array

• High-speed clock: 16 MHz

• Single supply voltage:

– 2.5 V to 5.5 V for M95512-W

– 1.8 V to 5.5 V for M95512-R and M95512-

– 1.7 V to 5.5 V for M95512-DF

• Operating temperature range: from -40°C up to

+85°C

• Enhanced ESD protection

• More than 4 million Write cycles

• More than 200-year data retention

• Packages

– RoHS compliant and halogen-free

(ECOPACK

)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

WLCSP (CS)

UFDFPN8

2 x 3 mm (MC)

(preliminary data)

www.st.com

Summary of content (50 pages)

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M95512-W M95512-R M95512-DR M95512-DF 512-Kbit serial SPI bus EEPROM Datasheet - production data Features • Compatible with the Serial Peripheral Interface (SPI) bus SO8 (MN) 150 mil width • Memory array – 512 Kb (64 Kbytes) of EEPROM – Page size: 128 bytes • Write – Byte Write within 5 ms – Page Write within 5 ms TSSOP8 (DW) 169 mil width • Additional Write lockable page (Identification page) • Write Protect: quarter, half or whole memory array • High-speed clock: 16 MHz UFDFPN8 2 x 3 mm (MC) • Singl
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Contents M95512-W M95512-R M95512-DR M95512-DF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 3.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.
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M95512-W M95512-R M95512-DR M95512-DF 6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.
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List of tables M95512-W M95512-R M95512-DR M95512-DF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. 4/50 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write-protected block size . . . . . .
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M95512-W M95512-R M95512-DR M95512-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Description 1 M95512-W M95512-R M95512-DR M95512-DF Description The M95512 devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as 65536 x 8 bits, accessed through the SPI bus. The M95512-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95512-R and M95512-DR can operate with a supply voltage from 1.8 V to 5.5 V, and the M95512-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C.
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M95512-W M95512-R M95512-DR M95512-DF Description Figure 2. 8-pin package connections (top view) M95xxx S Q W 1 2 3 4 VSS 8 7 6 5 VCC HOLD C D AI01790D 1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1. Figure 3.
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Memory organization 2 M95512-W M95512-R M95512-DR M95512-DF Memory organization The memory is organized as shown in the following figure. Figure 4.
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M95512-W M95512-R M95512-DR M95512-DF 3 Signal description Signal description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are described next. 3.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device.
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Signal description 3.6 M95512-W M95512-R M95512-DR M95512-DF Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all Write instructions. 3.7 VCC supply voltage VCC is the supply voltage. 3.
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M95512-W M95512-R M95512-DR M95512-DF 4 Connecting to the SPI bus Connecting to the SPI bus All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. All output data bytes are shifted out of the device, most significant bit first.
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Connecting to the SPI bus 4.1 M95512-W M95512-R M95512-DR M95512-DF SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two modes: • CPOL=0, CPHA=0 • CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C).
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M95512-W M95512-R M95512-DR M95512-DF 5 Operating features 5.1 Supply voltage (VCC) 5.1.1 Operating supply voltage (VCC) Operating features Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 9: DC and AC parameters).
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Operating features 5.1.4 M95512-W M95512-R M95512-DR M95512-DF Power-down During power-down (continuous decrease of the VCC supply voltage below the minimum VCC operating voltage defined under Operating conditions in Section 9: DC and AC parameters), the device must be: 5.2 • deselected (Chip Select S should be allowed to follow the voltage applied on VCC), • in Standby Power mode (there should not be any internal write cycle in progress).
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M95512-W M95512-R M95512-DR M95512-DF Operating features The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C) is already low (as shown in Figure 7). The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C) is already low. Figure 7 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. 5.
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Instructions 6 M95512-W M95512-R M95512-DR M95512-DF Instructions Each instruction starts with a single-byte code, as summarized in Table 3. If an invalid instruction is sent (one not contained in Table 3), the device automatically deselects itself. Table 3.
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M95512-W M95512-R M95512-DR M95512-DF 6.1 Instructions Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state.
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Instructions 6.2 M95512-W M95512-R M95512-DR M95512-DF Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 9, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high.
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M95512-W M95512-R M95512-DR M95512-DF 6.3 Instructions Read Status Register (RDSR) The Read Status Register (RDSR) instruction is used to read the Status Register. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 10.
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Instructions 6.3.4 M95512-W M95512-R M95512-DR M95512-DF SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal enable the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low).
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M95512-W M95512-R M95512-DR M95512-DF 6.4 Instructions Write Status Register (WRSR) The Write Status Register (WRSR) instruction is used to write new values to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must have been previously executed. The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low, followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S) driven high.
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Instructions M95512-W M95512-R M95512-DR M95512-DF Table 6. Protection modes W SRWD signal bit 1 0 0 0 1 1 0 1 Mode Write protection of the Status Register Memory content Protected area(1) Unprotected area(1) Status Register is writable (if the WREN instruction Softwarehas set the WEL bit). protected Write-protected The values in the BP1 (SPM) and BP0 bits can be changed. Ready to accept Write instructions Status Register is Hardware writeHardwareprotected.
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M95512-W M95512-R M95512-DR M95512-DF 6.5 Instructions Read from Memory Array (READ) As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). Figure 12.
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Instructions M95512-W M95512-R M95512-DR M95512-DF Figure 13. Byte Write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D 3 2 Data Byte 1 0 7 6 5 4 3 2 1 0 High Impedance Q AI01795D In the case of Figure 13, Chip Select (S) is driven high after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte.
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M95512-W M95512-R M95512-DR M95512-DF Instructions Figure 14. Page Write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 C Instruction 16-Bit Address 15 14 13 D 3 2 Data Byte 1 1 0 7 6 5 4 3 2 0 1 S 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 C Data Byte 2 7 D 6 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 2 Data Byte N 1 0 6 5 4 3 2 1 0 AI01796D 6.6.
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Instructions 6.7 M95512-W M95512-R M95512-DR M95512-DF Read Identification Page (available only in M95512-D devices) The Identification Page (128 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. Reading this page is achieved with the Read Identification Page instruction (see Table 4). The Chip Select signal (S) is first driven low, the bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D).
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M95512-W M95512-R M95512-DR M95512-DF 6.8 Instructions Write Identification Page (available only in M95512-D devices) The Identification Page (128 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. Writing this page is achieved with the Write Identification Page instruction (see Table 4). The Chip Select signal (S) is first driven low. The bits of the instruction byte, address bytes, and at least one data byte are then shifted in on Serial Data Input (D).
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Instructions 6.9 M95512-W M95512-R M95512-DR M95512-DF Read Lock Status (available only in M95512-D devices) The Read Lock Status instruction (see Table 4) is used to check whether the Identification Page is locked or not in Read-only mode. The Read Lock Status sequence is defined with the Chip Select (S) first driven low. The bits of the instruction byte and address bytes are then shifted in on Serial Data Input (D). Address bit A10 must be 1, all other address bits are Don't Care.
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M95512-W M95512-R M95512-DR M95512-DF 6.10 Instructions Lock ID (available only in M95512-D devices) The Lock ID instruction permanently locks the Identification Page in read-only mode. Before this instruction can be accepted, a Write Enable (WREN) instruction must have been executed. The Lock ID instruction is issued by driving Chip Select (S) low, sending the instruction code, the address and a data byte on Serial Data Input (D), and driving Chip Select (S) high.
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Power-up and delivery state M95512-W M95512-R M95512-DR M95512-DF 7 Power-up and delivery state 7.1 Power-up state After power-up, the device is in the following state: • Standby power mode, • deselected (after power-up, a falling edge is required on Chip Select (S) before any instructions can be started), • not in the Hold condition, • the Write Enable Latch (WEL) is reset to 0, • Write In Progress (WIP) is reset to 0.
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M95512-W M95512-R M95512-DR M95512-DF 8 Maximum rating Maximum rating Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7.
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DC and AC parameters 9 M95512-W M95512-R M95512-DR M95512-DF DC and AC parameters This section summarizes the operating conditions and the DC/AC characteristics of the device. Table 8. Operating conditions (M95512-W, device grade 6) Symbol VCC TA Parameter Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature –40 85 °C Table 9. Operating conditions (M95512-R and M95512-DR, device grade 6) Symbol VCC TA Parameter Min. Max. Unit Supply voltage 1.8 5.
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M95512-W M95512-R M95512-DR M95512-DF DC and AC parameters Table 12. Capacitance Test conditions(1) Min. Max. Unit VOUT = 0 V - 8 pF Input capacitance (D) VIN = 0 V - 8 pF Input capacitance (other pins) VIN = 0 V - 6 pF Symbol COUT CIN Parameter Output capacitance (Q) 1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz. Table 13. Cycling performance by groups of four bytes Symbol Ncycle Parameter(1) Write cycle endurance (2) Test conditions Min. Max.
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DC and AC parameters M95512-W M95512-R M95512-DR M95512-DF Table 15. DC characteristics (previous M95512-W products, device grade 6) Symbol Parameter Test conditions in addition to those defined in Table 8 (1) Min. Max. Unit ILI Input leakage current VIN = VSS or VCC - ±2 µA ILO Output leakage current S = VCC, VOUT = VSS or VCC - ±2 µA C = 0.1 VCC/0.9 VCC at 5 MHz, VCC = 2.5 V, Q = open - 3 ICC Supply current (Read) C = 0.1 VCC/0.
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M95512-W M95512-R M95512-DR M95512-DF DC and AC parameters Table 16. DC characteristics (M95512-W products, device grade 6) Symbol Parameter Test conditions in addition to those defined in Table 8 (1) Min. Max. Unit ILI Input leakage current VIN = VSS or VCC - ±2 µA ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC - ±2 µA ICC Supply current (Read) C = 0.1 VCC/0.9VCC at 10 MHz, VCC = 2.5 V, Q = open - 4 mA C = 0.1 VCC/0.
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DC and AC parameters M95512-W M95512-R M95512-DR M95512-DF Table 17. DC characteristics (M95512-R and M95512-DR products, device grade 6) Symbol Parameter Test conditions in addition to those defined in Table 9 (1) Min Max Unit ILI Input leakage current VIN = VSS or VCC - ±2 µA ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC - ±2 µA ICC Supply current (Read) C = 0.1 VCC/0.9 VCC at max clock frequency(2), VCC = 1.8 V, Q = open - 2.
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M95512-W M95512-R M95512-DR M95512-DF DC and AC parameters Table 18. DC characteristics (M95512-DF products, device grade 6) Symbol Parameter Test conditions in addition to those defined in Table 10 (1) Min Max Unit ILI Input leakage current VIN = VSS or VCC - ±2 µA ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC - ±2 µA ICC Supply current (Read) C = 0.1 VCC/0.9 VCC at 5 MHz, VCC = 1.7 V, Q = open - 2.
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DC and AC parameters M95512-W M95512-R M95512-DR M95512-DF Table 19. AC characteristics (previous M95512-W products, device grade 6) Test conditions: refer to Table 8 and Table 11 (1) Symbol Alt. Min. Max. Unit fC fSCK Clock frequency D.C.
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M95512-W M95512-R M95512-DR M95512-DF DC and AC parameters Table 20. AC characteristics (M95512-W products, device grade 6) Test conditions: refer to Table 8 and Table 11 (1) Min. Symbol Alt. Max. Min. Max. Parameter Unit 2.5 V to 5.5 V 4.5 V to 5.5 V D.C. 10 D.C.
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DC and AC parameters M95512-W M95512-R M95512-DR M95512-DF Table 21. AC characteristics (M95512-R and M95512-DF, device grade 6) Test conditions: refer to Table 9 or Table 10 and Table 11 (1)(2) Min. Min. Max. Symbol Alt. fC fSCK Clock frequency D.C. 2 D.C.
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M95512-W M95512-R M95512-DR M95512-DF DC and AC parameters Figure 20. Serial input timing tSHSL S tCHSL tCH tSLCH tCHSH tSHCH C tDVCH tCHCL tCL tCLCH tCHDX D Q LSB IN MSB IN High impedance AI01447d Figure 21. Hold timing S tHLCH tCLHL tHHCH C tCLHH tHLQZ tHHQV Q HOLD AI01448c Figure 22.
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Package mechanical data 10 M95512-W M95512-R M95512-DR M95512-DF Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 23. SO8N – 8-lead plastic small outline, 150 mils body width, package outline h x 45˚ A2 A c ccc b e 0.
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M95512-W M95512-R M95512-DR M95512-DF Package mechanical data Figure 24. TSSOP8 – 8-lead thin shrink small outline, package outline D 8 5 c E1 1 E 4 α A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 23. TSSOP8 – 8-lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A - - 1.200 - - 0.0472 A1 - 0.050 0.150 - 0.0020 0.0059 A2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b - 0.190 0.300 - 0.
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Package mechanical data M95512-W M95512-R M95512-DR M95512-DF Figure 25. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline e D b L1 L3 Pin 1 E E2 K L A D2 eee A1 ZW_MEeV2 1. Drawing is not to scale. 2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process. Table 24.
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M95512-W M95512-R M95512-DR M95512-DF Package mechanical data Figure 26. M95512-DFCS6TP/K – WLCSP 8-bump wafer-level chip scale package outline bbb Z D e1 e3 Y X Reference Reference e2 Detail A E e G aaa A A2 (4X) Wafer back side F Side view Bumps side Bump A1 eee Z b Øccc Øddd Z Seating plane M Z XY M Z Detail A Rotated 90 ° 1Cf_ME_V1 1. Drawing is not to scale.
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Package mechanical data M95512-W M95512-R M95512-DR M95512-DF Table 25. M95512-DFCS6TP/K, WLCSP 8-bump wafer-level chip scale package mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A 0.540 0.500 0.580 0.0213 0.0197 0.0228 A1 0.190 - - 0.0075 - - A2 0.350 - - 0.0138 - - b 0.270 - - 0.0106 - - D 1.271 - 1.291 0.0500 - 0.0508 E 1.937 - 1.957 0.0763 - 0.0770 e 1.000 - - 0.0394 - - e1 0.866 - - 0.0341 - - e2 0.500 - - 0.
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M95512-W M95512-R M95512-DR M95512-DF 11 Part numbering Part numbering Table 26. Ordering information scheme Example: Device type M95 = SPI serial access EEPROM M95512 W MN 6 T P /K Device function 512 = 512 Kbit (65536 x 8) 512-D = 512 Kbit plus Identification page Operating voltage W = VCC = 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V F = VCC = 1.7 to 5.
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Revision history 12 M95512-W M95512-R M95512-DR M95512-DF Revision history Table 27. Document revision history Date Revision Changes 01-Apr-2011 14 Added: – Table 14: Capacitance. – Note (1) under Table 23: DC characteristics (current and new M95080-R and M95080-DR products) – Notes (1) and (2) in Section 4.
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M95512-W M95512-R M95512-DR M95512-DF Revision history Table 27. Document revision history (continued) Date 18-Sep-2012 24-Sep-2012 06-Dec-2012 03-Jun-2013 Revision Changes 18 Fixed some errors in Figure 3: WLCSP connections for M95512DFCS6TP/K (top view, marking side, with bumps on the underside). Restored missing table: Table 10: Operating conditions (M95512-DF, device grade 6).
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M95512-W M95512-R M95512-DR M95512-DF Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.