Datasheet

DocID12276 Rev 20 25/52
M95256-W M95256-R M95256-DR M95256-DF Instructions
Figure 14. Page Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
6.6.1 Cycling with Error Correction Code (ECC)
M95256 and M95256-D devices offer an Error Correction Code (ECC) logic. The ECC is an
internal logic function which is transparent for the SPI communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes
(c)
. Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group
(c)
. As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the four bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in
Table 14.
C
D
AI01796D
S
3433 35 36 37 38 39 40 41 42 44 45 46 4732
C
D
S
15
21 345678910 2021222324252627
1413 3210
28 29 30
Instruction 16-Bit Address
0
765432 0
1
Data Byte 1
31
43
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3
65432 0
1
Data Byte N
c. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.