Datasheet

DocID12276 Rev 20 23/52
M95256-W M95256-R M95256-DR M95256-DF Instructions
6.5 Read from Memory Array (READ)
As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).
Figure 12. Read from Memory Array (READ) sequence
1. Depending on the memory size, as shown in Table 5, the most significant address bits are Don’t Care.
If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (
S) signal can occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.
6.6 Write to Memory Array (WRITE)
As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (
S) rising edge, continues for a
period t
W
(as specified in AC characteristics in Section 9: DC and AC parameters), at the
end of which the Write in Progress (WIP) bit is reset to 0.
C
D
AI01793D
S
Q
15
21 345678910 2021222324252627
1413 3210
28 29 30
76543 1 7
0
High Impedance
Data Out 1
Instruction 16-Bit Address
0
MSB
MSB
2
31
Data Out 2