Datasheet

DocID12276 Rev 20 39/52
M95256-W M95256-R M95256-DR M95256-DF DC and AC parameters
Table 21. AC characteristics (M95256-DF, device grade 6)
Test conditions specified in Table 11 and Table 12
Parameter
V
CC
≥ 1.7 V V
CC
≥ 2.5 V V
CC
≥ 4.5 V
Unit
Min. Max. Min. Max. Min. Max.
f
C
f
SCK
Clock frequency 5 10 20 MHz
t
SLCH
t
CSS1
S active setup time 60 30 15 ns
t
SHCH
t
CSS2
S not active setup time 60 30 15 ns
t
SHSL
t
CS
S deselect time 90 40 20 ns
t
CHSH
t
CSH
S active hold time 60 30 15 ns
t
CHSL
S not active hold time 60 30 15 ns
t
CH
(1)
t
CLH
Clock high time 80 40 20 ns
t
CL
(2)
t
CLL
Clock low time 80 40 20 ns
t
CLCH
(2)
t
RC
Clock rise time 2 2 2 µs
t
CHCL
t
FC
Clock fall time 2 2 2 µs
t
DVCH
t
DSU
Data in setup time 20 10 5 ns
t
CHDX
t
DH
Data in hold time 20 10 10 ns
t
HHCH
Clock low hold time after HOLD not active 60 30 15 ns
t
HLCH
Clock low hold time after HOLD active 60 30 15 ns
t
CLHL
Clock low setup time before HOLD active 0 0 0 ns
t
CLHH
Clock low setup time before HOLD not active 0 0 0 ns
t
SHQZ
t
DIS
Output disable time 80 40 20 ns
t
CLQV
t
V
Clock low to output valid 80 40 20 ns
t
CLQX
t
HO
Output hold time 0 0 0 ns
t
QLQH
t
RO
Output rise time 20 20 10 ns
t
QHQL
t
FO
Output fall time 20 20 10 ns
t
HHQV
t
LZ
HOLD high to output valid 80 40 20 ns
t
HLQZ
t
HZ
HOLD low to output High-Z 80 40 20 ns
t
W
t
WC
Write time 5 5 5 ms
1. t
CH
+ t
CL
must never be less than the shortest possible clock period, 1 / f
C
(max).
2. Characterized only, not tested in production.