Datasheet

DocID022540 Rev 2 25/44
M95080-W M95080-R M95080-DF Instructions
43
Note: The self-timed write cycle t
W
is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit
is read as “0” and a programmed bit is read as “1”.
Figure 13. Page Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 4, the most significant address bits are Don’t Care.
C
D
AI01796D
S
3433 35 36 37 38 39 40 41 42 44 45 46 4732
C
D
S
15
21 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27
14 13 3 2 1 0
28 29 30
Instruction 16-Bit Address
0
765432 0
1
Data Byte 1
31
43
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3
65432 0
1
Data Byte N