M95080-W M95080-R M95080-DF 8-Kbit serial SPI bus EEPROM with high-speed clock Datasheet - production data Features • Compatible with the Serial Peripheral Interface (SPI) bus SO8 (MN) 150 mil width • Memory array – 8 Kb (1 Kbyte) of EEPROM – Page size: 32 bytes • Write – Byte Write within 5 ms – Page Write within 5 ms • Write Protect: quarter, half or whole memory array TSSOP8 (DW) 169 mil width UFDFPN8 (MC) 2 x 3 mm • High-speed clock: 20 MHz • Single supply voltage: – 2.5 V to 5.
Contents M95080-W M95080-R M95080-DF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 3.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.
M95080-W M95080-R M95080-DF 7 Contents 6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.
List of tables M95080-W M95080-R M95080-DF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. 4/44 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M95080-W M95080-R M95080-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections (top view) . . . . . . . . . . .
Description 1 M95080-W M95080-R M95080-DF Description The M95080 devices are Electrically Erasable PROgrammable Memories (EEPROMs) organized as 1024 x 8 bits, accessed through the SPI bus. The M95080-W can operate with a supply voltage from 2.5 V to 5.5 V, the M95080-R can operate with a supply voltage from 1.8 V to 5.5 V, and the M95080-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C.
M95080-W M95080-R M95080-DF Description Figure 2. 8-pin package connections (top view) M95xxx S 1 Q 2 W 3 VSS 4 8 7 6 5 VCC HOLD C D AI01790D 1. See Section 10: Package mechanical data for package dimensions, and how to identify pin-1.
Memory organization 2 M95080-W M95080-R M95080-DF Memory organization The memory is organized as shown in the following figure. Figure 3.
M95080-W M95080-R M95080-DF 3 Signal description Signal description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals must be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are described next. 3.1 Serial Data Output (Q) This output signal is used to transfer data serially out of the device.
Signal description 3.6 M95080-W M95080-R M95080-DF Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against Write instructions (as specified by the values in the BP1 and BP0 bits of the Status Register). This pin must be driven either high or low, and must be stable during all Write instructions. 3.7 VCC supply voltage VCC is the supply voltage. 3.8 VSS ground VSS is the reference for all signals, including the VCC supply voltage.
M95080-W M95080-R M95080-DF 4 Connecting to the SPI bus Connecting to the SPI bus All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. All output data bytes are shifted out of the device, most significant bit first.
Connecting to the SPI bus 4.1 M95080-W M95080-R M95080-DF SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the following two modes: • CPOL=0, CPHA=0 • CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C).
M95080-W M95080-R M95080-DF Operating features 5 Operating features 5.1 Supply voltage (VCC) 5.1.1 Operating supply voltage (VCC) Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 9: DC and AC parameters).
Operating features 5.1.4 M95080-W M95080-R M95080-DF Power-down During power-down (continuous decrease of the VCC supply voltage below the minimum VCC operating voltage defined under Operating conditions in Section 9: DC and AC parameters), the device must be: 5.2 • deselected (Chip Select S should be allowed to follow the voltage applied on VCC), • in Standby Power mode (there should not be any internal write cycle in progress).
M95080-W M95080-R M95080-DF Operating features The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C) is already low (as shown in Figure 6). Figure 6 also shows what happens if the rising and falling edges are not timed to coincide with Serial Clock (C) being low. 5.4 Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. See Section 6.
Instructions 6 M95080-W M95080-R M95080-DF Instructions Each command is composed of bytes (MSBit transmitted first), initiated with the instruction byte, as summarized in Table 3. If an invalid instruction is sent (one not contained in Table 3), the device automatically enters a Wait state until deselected. Table 3.
M95080-W M95080-R M95080-DF 6.1 Instructions Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state.
Instructions 6.2 M95080-W M95080-R M95080-DF Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high.
M95080-W M95080-R M95080-DF 6.3 Instructions Read Status Register (RDSR) The Read Status Register (RDSR) instruction is used to read the Status Register. The Status Register may be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 9. Figure 9.
Instructions 6.3.4 M95080-W M95080-R M95080-DF SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal enable the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low).
M95080-W M95080-R M95080-DF 6.4 Instructions Write Status Register (WRSR) The Write Status Register (WRSR) instruction is used to write new values to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must have been previously executed. The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low, followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S) driven high.
Instructions M95080-W M95080-R M95080-DF Table 6. Protection modes W SRWD signal bit 1 0 0 0 1 1 0 1 Mode Write protection of the Status Register Memory content Protected area(1) Unprotected area(1) Status Register is writable (if the WREN instruction Softwarehas set the WEL bit). protected Write-protected The values in the BP1 (SPM) and BP0 bits can be changed. Ready to accept Write instructions Status Register is Hardware writeHardwareprotected.
M95080-W M95080-R M95080-DF 6.5 Instructions Read from Memory Array (READ) As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data Input (D). The address is loaded into an internal address register, and the byte of data at that address is shifted out, on Serial Data Output (Q). Figure 11.
Instructions 6.6 M95080-W M95080-R M95080-DF Write to Memory Array (WRITE) As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data Input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data.
M95080-W M95080-R M95080-DF Note: Instructions The self-timed write cycle tW is internally executed as a sequence of two consecutive events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is read as “0” and a programmed bit is read as “1”. Figure 13.
Instructions 6.7 M95080-W M95080-R M95080-DF Read Identification Page (available only in M95080-D devices) The Read Identification Page (RDID) instruction is used to read the Identification Page (additional page of 32 bytes which can be written and later permanently locked in Read-only mode). The Chip Select (S) signal is first driven low, the bits of the instruction byte and address bytes are then shifted in (MSB first) on Serial Data input (D).
M95080-W M95080-R M95080-DF 6.8 Instructions Write Identification Page (available only in M95080-D devices) The Write Identification Page (WRID) instruction is used to write the Identification Page (additional page of 32 bytes which can also be permanently locked in Read-only mode). The Chip Select signal (S) is first driven low, and then the bits of the instruction byte, address bytes, and at least one data byte are shifted in (MSB first) on Serial Data input (D).
Instructions 6.9 M95080-W M95080-R M95080-DF Read Lock Status (available only in M95080-D devices) The Read Lock Status (RDLS) instruction is used to read the lock status. To send this instruction to the device, Chip Select (S) first has to be driven low. The bits of the instruction byte and address bytes are then shifted in (MSB first) on Serial Data input (D). Address bit A10 must be 1; all other address bits are Don't Care (it might be easier to define these bits as 0, as shown in Table 4).
M95080-W M95080-R M95080-DF 6.10 Instructions Lock ID (available only in M95080-D devices) The Lock Identification Page (LID) command is used to permanently lock the Identification Page in Read-only mode. The LID instruction is issued by driving Chip Select (S) low, sending (MSB first) the instruction code, the address and a data byte on Serial Data input (D), and driving Chip Select (S) high. In the address sent, A10 must be equal to 1.
Power-up and delivery state M95080-W M95080-R M95080-DF 7 Power-up and delivery state 7.1 Power-up state After power-up, the device is in the following state: • Standby power mode, • deselected (after power-up, a falling edge is required on Chip Select (S) before any instructions can be started), • not in the Hold condition, • the Write Enable Latch (WEL) is reset to 0, • Write In Progress (WIP) is reset to 0.
M95080-W M95080-R M95080-DF 8 Maximum rating Maximum rating Stressing the device outside the ratings listed in Table 7 may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7.
DC and AC parameters 9 M95080-W M95080-R M95080-DF DC and AC parameters This section summarizes the operating conditions and the DC/AC characteristics of the device. Table 8. Operating conditions (M95080-W, device grade 6) Symbol VCC TA Parameter Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature –40 85 °C Table 9. Operating conditions (M95080-R, device grade 6) Symbol VCC TA Parameter Min. Max. Unit Supply voltage 1.8 5.
M95080-W M95080-R M95080-DF DC and AC parameters Table 11. AC measurement conditions Symbol CL Parameter Min. Max. Load capacitance 30 Input rise and fall times - Unit pF 50 ns Input pulse voltages 0.2 VCC to 0.8 VCC V Input and output timing reference voltages 0.3 VCC to 0.7 VCC V Figure 18. AC measurement I/O waveform Input voltage levels Input and output timing reference levels 0.8 VCC 0.7 VCC 0.3 VCC 0.2 VCC AI00825C Table 12.
DC and AC parameters M95080-W M95080-R M95080-DF Table 15. DC characteristics (M95080-W, device grade 6) Symbol Parameter Test conditions in addition to those defined in Max. Unit ILI Input leakage current VIN = VSS or VCC - ±2 µA ILO Output leakage current S = VCC, VOUT = VSS or VCC - ±2 µA VCC = 2.5 V, fC = 5 MHz, C = 0.1 VCC/0.9 VCC, Q = open - 2 VCC = 2.5 V, fC = 10 MHz, C = 0.1 VCC/0.9 VCC, Q = open - 2 (1) VCC = 5.5 V, fC = 20 MHz, C = 0.1 VCC/0.
M95080-W M95080-R M95080-DF DC and AC parameters Table 16. DC characteristics (M95080-R or M95080-DF, device grade 6) Symbol Parameter Test conditions in addition to those defined in in Table 9 or Table 10 and Table 11(1) Min. Max. Unit ILI Input leakage current VIN = VSS or VCC - ±2 µA ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC - ±2 µA ICC Supply current (Read) VCC = 1.8 V or 1.7 V, fC = 5 MHz, C = 0.1 VCC/0.
DC and AC parameters M95080-W M95080-R M95080-DF Table 17. AC characteristics (M95080-W, device grade 6) Test conditions specified in Table 8 and Table 11 (1) Symbol Alt. Parameter VCC = 2.5 to 5.5 V VCC = 4.5 to 5.5 V Unit Min. Max. Min. Max. D.C. 10 D.C.
M95080-W M95080-R M95080-DF DC and AC parameters Table 18. AC characteristics (M95080-R or M95080-DF, device grade 6) Test conditions specified in Table 9 or Table 10 and Table 11(1) Symbol Alt. Parameter fSCK Clock frequency fC Min. Max. Unit D.C.
DC and AC parameters M95080-W M95080-R M95080-DF Figure 19. Serial input timing tSHSL S tCHSL tCH tSLCH tCHSH tSHCH C tDVCH tCL tCHCL tCLCH tCHDX LSB IN MSB IN D High impedance Q AI01447d Figure 20. Hold timing S tHLCH tCLHL tHHCH C tCLHH tHLQZ tHHQV Q AI01448c Figure 21.
M95080-W M95080-R M95080-DF 10 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 22. SO8N – 8-lead plastic small outline, 150 mils body width, package outline h x 45° A2 A c ccc b e 0.
Package mechanical data M95080-W M95080-R M95080-DF Figure 23. TSSOP8 – 8-lead thin shrink small outline, package outline D 8 5 c E1 E 4 1 a A1 A A2 L L1 CP e b TSSOP8AM 1. Drawing is not to scale. Table 20. TSSOP8 – 8-lead thin shrink small outline, package mechanical data inches(1) millimeters Symbol Typ Min Max Typ Min Max A - - 1.200 - - 0.0472 A1 - 0.050 0.150 - 0.0020 0.0059 A2 1.000 0.800 1.050 0.0394 0.0315 0.0413 b - 0.190 0.300 - 0.0075 0.
M95080-W M95080-R M95080-DF Package mechanical data Figure 24. UFDFPN8 (MLP8) – 8-lead ultra thin fine pitch dual flat no lead, package outline D MC e b L1 L3 Pin 1 E E2 K L A D2 eee A1 ZW_MEeV2 1. Drawing is not to scale. 2. The central pad (area E2 by D2 in the above illustration) is internally pulled to VSS. It must not be connected to any other voltage or signal line on the PCB, for example during the soldering process. Table 21.
Part numbering 11 M95080-W M95080-R M95080-DF Part numbering Table 22. Ordering information scheme Example: M95080-D W MN 6 T P \S Device type M95 = SPI serial access EEPROM Device function 080 = 8 Kbit (1024 x 8) 080-D = 8 Kbit (1024 x 8) plus identification page Operating voltage W = VCC = 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V F = VCC = 1.7 to 5.
M95080-W M95080-R M95080-DF 12 Revision history Revision history Table 23. Document revision history Date Revision 22-Mar-2012 1 Initial release. 2 Replaced “M95080” by “M95080-DF” part number. Updated: – Package figure on cover page – Features: Single supply voltage, high-speed clock frequency, write cycles and data retention – Section 1: Description – Figure 3: Block diagram – Section 6: Instructions: updated introduction and added Section 6.7 to Section 6.10 – Section 7.
M95080-W M95080-R M95080-DF Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.
