Datasheet

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M950x0-W M950x0-R M950x0-DF DC and AC parameters
44
Table 18. AC characteristics (M950x0-W, device grade 6)
(1)
Test conditions specified in Table 9 and Table 12
Symbol Alt. Parameter
V
CC
= 2.5 to 5.5 V
(2)
V
CC
= 4.5 to 5.5 V
Unit
Min. Max. Min. Max.
f
C
f
SCK
Clock frequency D.C. 10 D.C. 20 MHz
t
SLCH
t
CSS1
S active setup time 30 - 15 - ns
t
SHCH
t
CSS2
S not active setup time 30 - 15 - ns
t
SHSL
t
CS
S deselect time 40 - 20 - ns
t
CHSH
t
CSH
S active hold time 30 - 15 - ns
t
CHSL
S not active hold time 30 - 15 - ns
t
CH
(3)
t
CLH
Clock high time 40 - 20 - ns
t
CL
(3)
t
CLL
Clock low time 40 - 20 - ns
t
CLCH
(4)
t
RC
Clock rise time - 2 - 2 µs
t
CHCL
(4)
t
FC
Clock fall time - 2 - 2 µs
t
DVCH
t
DSU
Data in setup time 10 - 5 - ns
t
CHDX
t
DH
Data in hold time 10 - 10 - ns
t
HHCH
Clock low hold time after HOLD not active 30 - 15 - ns
t
HLCH
Clock low hold time after HOLD active 30 - 15 - ns
t
CLHL
Clock low set-up time before HOLD active 0 - 0 - ns
t
CLHH
Clock low set-up time before HOLD not active 0 - 0 ns
t
SHQZ
(4)
t
DIS
Output disable time - 40 - 20 ns
t
CLQV
(5)
t
V
Clock low to output valid - 40 - 20 ns
t
CLQX
t
HO
Output hold time 0 - 0 - ns
t
QLQH
(4)
t
RO
Output rise time - 40 - 20 ns
t
QHQL
(4)
t
FO
Output fall time - 40 - 20 ns
t
HHQV
t
LZ
HOLD high to output valid - 40 - 20 ns
t
HLQZ
(4)
t
HZ
HOLD low to output high-Z - 40 - 20 ns
t
W
t
WC
Write time - 5 - 5 ms
1. The timing values described in this table are recommended for new designs.
2. Only for devices identified by process letter K.
3. t
CH
+ t
CL
must never be lower than the shortest possible clock period, 1/f
C
(max).
4. Characterized only, not tested in production.
5. t
CLQV
must be compatible with t
CL
(clock low time): if the SPI bus master offers a Read setup time t
SU
= 0 ns, t
CL
can be
equal to (or greater than) t
CLQV
; in all other cases, t
CL
must be equal to (or greater than) t
CLQV
+t
SU
.