Datasheet

Connecting to the SPI bus M950x0-W M950x0-R M950x0-DF
12/45 DocID6512 Rev 12
3.1 SPI modes
The device can be driven by a microcontroller with its SPI peripheral running in either of the
following modes:
 CPOL=0, CPHA=0
 CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4: SPI modes supported, is the
clock polarity when the bus master is in Stand-by mode and not transferring data:
 C remains at 0 for (CPOL=0, CPHA=0)
 C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. SPI modes supported
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB