Datasheet

DocID6512 Rev 12 29/45
M950x0-W M950x0-R M950x0-DF Power-up and delivery states
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7 Power-up and delivery states
7.1 Power-up state
After Power-up, the device is in the following state:
 Low power Standby Power mode
 Deselected (after Power-up, a falling edge is required on Chip Select (S
) before any
instructions can be started)
 Not in Hold Condition
 Write Enable Latch (WEL) is reset to 0
 Write In Progress (WIP) is reset to 0
The BP1 and BP0 bits of the Status register are unchanged from the previous power-down
(they are non-volatile bits).
7.2 Initial delivery state
The device is delivered with:
 the memory array set to all 1s (each byte = FFh)
 Status register: bit SRWD =0, BP1 =0 and BP0 =0
 M95040-D only: the identification page bytes values are Don’t Care.