Datasheet

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This is information on a product in full production.

October 2013 DocID6512 Rev 12 1/45

M950x0-W M950x0-R M950x0-DF

4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM

with high-speed clock

Datasheet - production data

Features

 Compatible with SPI bus serial interface

(Positive clock SPI modes)

 Single supply voltage:

– 2.5 V to 5.5 V for M950x0-W

– 1.8 V to 5.5 V for M950x0-R

– 1.7 V to 5.5 V for M95040-DF

 High-speed 20 MHz clock rate, 5 ms write time

 Memory array:

– 1/2/4 Kbit (128/256/512 bytes) of EEPROM

– Page size: 16 bytes

– Write protection by block: 1/4, 1/2 or whole

memory

– Additional Write lockable Page

(Identification page)

 Enhanced ESD protection

 More than 4 million write cycles

 More than 200-year data retention

 Packages RoHS-compliant and Halogen-free

(ECOPACK®)

SO8 (MN)

150 mil width

TSSOP8 (DW)

169 mil width

UFDFPN8 (MC)

2 x 3 mm

Table 1. Device summary

Reference Part number

M950x0-W

M95040-W

M95020-W

M95010-W

M950x0-R

M95040-R

M95020-R

M95010-R

M950x0-DF M95040-DF

www.st.com

Summary of content (45 pages)

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M950x0-W M950x0-R M950x0-DF 4 Kbit, 2 Kbit and 1 Kbit serial SPI bus EEPROM with high-speed clock Datasheet - production data Features  Compatible with SPI bus serial interface (Positive clock SPI modes) SO8 (MN) 150 mil width TSSOP8 (DW) 169 mil width  Single supply voltage: – 2.5 V to 5.5 V for M950x0-W – 1.8 V to 5.5 V for M950x0-R – 1.7 V to 5.
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Contents M950x0-W M950x0-R M950x0-DF Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 2.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.
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M950x0-W M950x0-R M950x0-DF 7 Contents 6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.7 Read Identification Page (available only in M95040-D device) . . . . . . . . 25 6.8 Write Identification Page (available only in M95040-D device) . . . . . . .
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List of tables M950x0-W M950x0-R M950x0-DF List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. 4/45 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . .
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M950x0-W M950x0-R M950x0-DF List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8-pin package connections . . . . . . . . . . . . . . . .
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Description 1 M950x0-W M950x0-R M950x0-DF Description The M95010/ M95020/M95040 devices (M950x0) are electrically erasable programmable memories (EEPROMs) organized as 128/256/512 x 8 bits respectively, accessed through the SPI bus. The M950x0-W can operate with a supply voltage from 2.5 V to 5.5 V, the M950x0-R can operate with a supply voltage from 1.8 V to 5.5 V, and the M950x0-DF can operate with a supply voltage from 1.7 V to 5.5 V, over an ambient temperature range of -40 °C / +85 °C.
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M950x0-W M950x0-R M950x0-DF Description Table 2.
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Signal description 2 M950x0-W M950x0-R M950x0-DF Signal description During all operations, VCC must be held stable and within the specified valid range: VCC(min) to VCC(max). All of the input and output signals can be held high or low (according to voltages of VIH, VOH, VIL or VOL, as specified in Table 16: DC characteristics (M950x0-W, device grade 6) and Table 17: DC characteristics (M950x0-R or M95040-DF, device grade 6). These signals are described next. 2.
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M950x0-W M950x0-R M950x0-DF 2.6 Signal description Write Protect (W) This input signal controls whether the memory is write protected. When Write Protect (W) is held low, writes to the memory are disabled, but other operations remain enabled.  Write Protect (W) must either be driven high or low, but must not be left floating. 2.7 VSS ground VSS is the reference for the VCC supply voltage. 2.8 Supply voltage (VCC) 2.8.
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Signal description 2.8.3 M950x0-W M950x0-R M950x0-DF Power-up conditions When the power supply is turned on, VCC rises continuously from VSS to VCC. During this time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see Figure 3: Bus master and memory devices on the SPI bus).
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M950x0-W M950x0-R M950x0-DF 3 Connecting to the SPI bus Connecting to the SPI bus The device is fully compatible with the SPI protocol. All instructions, addresses and input data bytes are shifted in to the device, most significant bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes low. All output data bytes are shifted out of the device, most significant bit first.
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Connecting to the SPI bus 3.1 M950x0-W M950x0-R M950x0-DF SPI modes The device can be driven by a microcontroller with its SPI peripheral running in either of the following modes:  CPOL=0, CPHA=0  CPOL=1, CPHA=1 For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock (C).
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M950x0-W M950x0-R M950x0-DF Operating features 4 Operating features 4.1 Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care. To enter the Hold condition, the device must be selected, with Chip Select (S) low.
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Operating features 4.3 M950x0-W M950x0-R M950x0-DF Data protection and protocol control To help protect the device from data corruption in noisy or poorly controlled environments, a number of safety features have been built in to the device. The main security measures can be summarized as follows:  WEL bit is reset at power-up.  Chip Select (S) must rise after the eighth clock count (or multiple thereof) in order to start a non-volatile Write cycle (in the memory array or in the Status register).
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M950x0-W M950x0-R M950x0-DF Memory organization The memory is organized as shown in Figure 6. Figure 6.
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Instructions 6 M950x0-W M950x0-R M950x0-DF Instructions Each command is composed of bytes (MSBit transmitted first), initiated with the instruction byte, as summarized in Table 4. If an invalid instruction is sent (one not contained in Table 4), the device automatically enters a Wait state until deselected. Table 4.
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M950x0-W M950x0-R M950x0-DF 6.1 Instructions Write Enable (WREN) The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction. The only way to do this is to send a Write Enable instruction to the device. As shown in Figure 7: Write Enable (WREN) sequence, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state.
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Instructions 6.2 M950x0-W M950x0-R M950x0-DF Write Disable (WRDI) One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction to the device. As shown in Figure 8: Write Disable (WRDI) sequence, to send this instruction to the device, Chip Select (S) is driven low, and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then enters a wait state. It waits for a the device to be deselected, by Chip Select (S) being driven high.
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M950x0-W M950x0-R M950x0-DF 6.3 Instructions Read Status Register (RDSR) The Read Status Register instruction is used to read the Status Register. As shown in Figure 9, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte are then shifted in, on Serial Data Input (D). The current state of the bits in the Status register is shifted out, on Serial Data Out (Q). The Read Cycle is terminated by driving Chip Select (S) high.
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Instructions 6.3.3 M950x0-W M950x0-R M950x0-DF BP1, BP0 bits The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Write instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3: Write-protected block size) becomes protected against Write (WRITE) instructions.
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M950x0-W M950x0-R M950x0-DF 6.4 Instructions Write Status Register (WRSR) A Write Status Register (WRSR) instruction allows new values to be written to the Status register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. The WRSR instruction is entered by driving Chip Select (S) low, sending the instruction code followed by the data byte on Serial Data input (D), and driving the Chip Select (S) signal high.
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Instructions 6.5 M950x0-W M950x0-R M950x0-DF Read from Memory Array (READ) As shown in Figure 11: Read from Memory Array (READ) sequence, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte and address byte are then shifted in, on Serial Data Input (D). For the M95040, the most significant address bit, A8, is incorporated as bit b3 of the instruction byte, as shown in Table 4: Instruction set.
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M950x0-W M950x0-R M950x0-DF 6.6 Instructions Write to Memory Array (WRITE) As shown in Figure 12: Byte Write (WRITE) sequence, to send this instruction to the device, Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least one data byte are then shifted in, on Serial Data input (D). The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input data.
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Instructions M950x0-W M950x0-R M950x0-DF Figure 13. Page Write (WRITE) sequence S 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 C Instruction Byte Address A8 D Data Byte 1 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0 7 142 143 141 140 139 138 137 136 15+8N 14+8N 13+8N 12+8N 11+8N 10+8N 9+8N 24 25 26 27 28 29 30 31 8+8N S 1 0 C Data Byte 2 D 7 6 5 4 3 2 Data Byte N 1 0 7 6 5 4 3 2 Data Byte 16 1 0 7 6 5 4 3 2 AI01443D 1.
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M950x0-W M950x0-R M950x0-DF 6.7 Instructions Read Identification Page (available only in M95040-D device) The Read Identification Page (RDID) instruction is used to read the Identification Page (additional page of 16 bytes which can be written and later permanently locked in Read-only mode). The Chip Select (S) signal is first driven low, the bits of the instruction byte and address bytes are then shifted in (MSB first) on Serial Data input (D).
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Instructions 6.8 M950x0-W M950x0-R M950x0-DF Write Identification Page (available only in M95040-D device) The Write Identification Page (WRID) instruction is used to write the Identification Page (additional page of 16 bytes which can also be permanently locked in Read-only mode). The Chip Select signal (S) is first driven low, and then the bits of the instruction byte, address bytes, and at least one data byte are shifted in (MSB first) on Serial Data input (D).
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M950x0-W M950x0-R M950x0-DF 6.9 Instructions Read Lock Status (available only in M95040-D device) The Read Lock Status (RDLS) instruction is used to read the lock status. To send this instruction to the device, Chip Select (S) first has to be driven low. The bits of the instruction byte and address bytes are then shifted in (MSB first) on Serial Data input (D). Address bit A7 must be 1; all other address bits are Don't Care (it might be easier to define these bits as 0, as shown in Table 5).
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Instructions 6.10 M950x0-W M950x0-R M950x0-DF Lock Identification Page (available only in M95040-D device) The Lock Identification Page (LID) command is used to permanently lock the Identification Page in Read-only mode. The LID instruction is issued by driving Chip Select (S) low, sending (MSB first) the instruction code, the address and a data byte on Serial Data input (D), and driving Chip Select (S) high. In the address sent, A7 must be equal to 1.
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M950x0-W M950x0-R M950x0-DF Power-up and delivery states 7 Power-up and delivery states 7.
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Maximum rating 8 M950x0-W M950x0-R M950x0-DF Maximum rating Stressing the device outside the ratings listed in Table 8: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 8.
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M950x0-W M950x0-R M950x0-DF 9 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. Table 9. Operating conditions (M950x0-W) Symbol VCC TA Parameter Min. Max. Unit Supply voltage 2.5 5.5 V Ambient operating temperature (device grade 6) –40 85 °C Min. Max. Unit Supply voltage 1.8 5.5 V Ambient operating temperature –40 85 °C Table 10.
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DC and AC parameters M950x0-W M950x0-R M950x0-DF Table 13. Cycling performance(1) Symbol Ncycle Parameter Write cycle endurance Test conditions Min. Max. Unit TA  25 °C, VCC(min) < VCC < VCC(max) - 4,000,000 TA = 85 °C, VCC(min) < VCC < VCC(max) - Write cycle 1,200,000 1. Cycling performance for products identified by process letter K. Table 14. Memory cell data retention(1) Parameter Test conditions Data retention Min. Unit 200 Year TA = 55 °C 1.
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M950x0-W M950x0-R M950x0-DF DC and AC parameters Table 16. DC characteristics (M950x0-W, device grade 6) Symbol Parameter Test conditions in addition to those defined in Table 9 Min. Max. Unit ILI Input leakage current VIN = VSS or VCC - ±2 µA ILO Output leakage current S = VCC, VOUT = VSS or VCC - ±2 µA VCC = 2.5 V, fC = 5 MHz, C = 0.1 VCC/0.9 VCC, Q = open - 2 VCC = 2.5 V, fC = 10 MHz, C = 0.1 VCC/0.9 VCC, Q = open - 2 VCC = 5.5 V, fC = 20 MHz, C = 0.1 VCC/0.
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DC and AC parameters M950x0-W M950x0-R M950x0-DF Table 17. DC characteristics (M950x0-R or M95040-DF, device grade 6) Symbol Parameter Test conditions in addition to those defined in in Table 10 or Table 11 and Table 12(1) Min. Max. Unit ILI Input leakage current VIN = VSS or VCC - ±2 µA ILO Output leakage current S = VCC, voltage applied on Q = VSS or VCC - ±2 µA ICC Supply current (Read) VCC = 1.8 V or 1.7 V, fC = 5 MHz, C = 0.1 VCC/0.
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M950x0-W M950x0-R M950x0-DF DC and AC parameters Table 18. AC characteristics (M950x0-W, device grade 6)(1) Test conditions specified in Table 9 and Table 12 (2) Symbol Alt. Parameter VCC = 2.5 to 5.5 V VCC = 4.5 to 5.5 V Unit Min. Max. Min. Max. D.C. 10 D.C.
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DC and AC parameters M950x0-W M950x0-R M950x0-DF Table 19. AC characteristics (M950x0-R or M95040-DF, device grade 6)(1) Test conditions specified in Table 10 or Table 11 and Table 12(2) Symbol fC Alt. Parameter fSCK Clock frequency Min. Max. Unit D.C.
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M950x0-W M950x0-R M950x0-DF DC and AC parameters Table 20. AC characteristics (M950x0-W, device grade 6) Not recommended for new designs, for new designs refer to Table 18 Test conditions specified in Table 9 and Table 12 Symbol Alt. Min. Max. Unit fC fSCK Clock frequency D.C.
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DC and AC parameters M950x0-W M950x0-R M950x0-DF Table 21. AC characteristics (M950x0-R, device grade 6) Not recommended for new designs, for new designs refer to Table 19 Test conditions specified in Table 10 and Table 12(1) Symbol Alt. Min. Max. Unit fC fSCK Clock frequency D.C.
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M950x0-W M950x0-R M950x0-DF DC and AC parameters Figure 19. Serial input timing tSHSL S tCHSL tCH tSLCH tCHSH tSHCH C tDVCH tCL tCHCL tCLCH tCHDX LSB IN MSB IN D High impedance Q AI01447d Figure 20. Hold timing S tHLCH tCLHL tHHCH C tCLHH tHLQZ tHHQV Q AI01448c Figure 21.
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Package mechanical data 10 M950x0-W M950x0-R M950x0-DF Package mechanical data In order to meet environmental requirements, ST offers the device in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 22. SO8N 8-lead plastic small outline 150 mils body width, package outline h x 45° A2 A c ccc b e 0.
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M950x0-W M950x0-R M950x0-DF Package mechanical data Figure 23. TSSOP8 8-lead thin shrink small outline, package outline D 8 5 c E1 E 4 1 a A1 A L A2 L1 CP b e TSSOP8AM 1. Drawing is not to scale. Table 23. TSSOP8 8-lead thin shrink small outline, package mechanical data Inches(1) Millimeters Symbol Typ. Min. Max. Typ. Min. Max. A - - 1.2 - - 0.0472 A1 - 0.05 0.15 - 0.002 0.0059 A2 1 0.8 1.05 0.0394 0.0315 0.0413 b - 0.19 0.3 - 0.0075 0.0118 c - 0.09 0.
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Package mechanical data M950x0-W M950x0-R M950x0-DF Figure 24. UFDFPN8 (MLP8) 8-lead ultra thin fine pitch dual flat package no lead 2 × 3mm, outline D MC e b L1 L3 Pin 1 E E2 K L A D2 eee A1 ZW_MEeV2 1. Drawing is not to scale. 2. The central pad (area E2 by D2 in the above illustration) is pulled, internally, to VSS. It must not be allowed to be connected to any other voltage or signal line on the PCB, for example during the soldering process. 3.
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M950x0-W M950x0-R M950x0-DF 11 Part numbering Part numbering Table 25. Ordering information scheme  Example: M95040-D – W MN 6 T P Device type M95 = SPI serial access EEPROM Device function 040 = 4 Kbit (512 x 8) 040-D = 4 Kbit (512 x 8) plus identification page 020 = 2 Kbit (256 x 8) 010 = 1 Kbit (128 x 8) Operating voltage W = VCC = 2.5 to 5.5 V R = VCC = 1.8 to 5.5 V F = VCC = 1.7 to 5.
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Revision history 12 M950x0-W M950x0-R M950x0-DF Revision history Table 26. Document revision history Date 02-Feb-2012 24-May-2013 17-Oct-2013 44/45 Version Changes 10 Document renamed from “M95040 M95020 M95010” to “M950x0 M950x0-W M950x0-R” Silhouette of UDFPN8 (MB or MC) on the cover page updated. Section 6.3: Read Status Register (RDSR) updated. Text modified in Section 6.3.1: WIP bit. Table 8: Absolute maximum ratings updated.
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M950x0-W M950x0-R M950x0-DF  Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.