Datasheet
DocID6512 Rev 12 23/45
M950x0-W M950x0-R M950x0-DF Instructions
44
6.6 Write to Memory Array (WRITE)
As shown in Figure 12: Byte Write (WRITE) sequence, to send this instruction to the device,
Chip Select (S) is first driven low. The bits of the instruction byte, address byte, and at least
one data byte are then shifted in, on Serial Data input (D). The instruction is terminated by
driving Chip Select (
S) high at a byte boundary of the input data. The self-timed Write cycle,
triggered by the rising edge of Chip Select (
S), continues for a period t
W
(as specified in
Table 16: DC characteristics (M950x0-W, device grade 6) to Table 19: AC characteristics
(M950x0-R or M95040-DF, device grade 6)). After this time, the Write in Progress (WIP) bit
is reset to 0.
In the case of Figure 12: Byte Write (WRITE) sequence, Chip Select (S) is driven high after
the eighth bit of the data byte has been latched in, indicating that the instruction is being
used to write a single byte. If, though, Chip Select (
S) continues to be driven low, as shown
in
Figure 13: Page Write (WRITE) sequence, the next byte of input data is shifted in, so that
more than a single byte, starting from the given address towards the end of the same page,
can be written in a single internal Write cycle. If Chip Select (
S) still continues to be driven
low, the next byte of input data is shifted in, and used to overwrite the byte at the start of the
current page.
The instruction is not accepted, and is not executed, under the following conditions:
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
if a Write cycle is already in progress
if the device has not been deselected, by Chip Select (S
) being driven high, at a byte
boundary (after the rising edge of Serial Clock (C) that latches the last data bit, and
before the next rising edge of Serial Clock (C) occurs anywhere on the bus)
if Write Protect (W
) is low or if the addressed page is in the area protected by the Block
Protect (BP1 and BP0) bits
Note: The self-timed write cycle t
W
is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit
is read as “0” and a programmed bit is read as “1”.
Figure 12. Byte Write (WRITE) sequence
1. Depending on the memory size, as shown in Table 7: Address range bits, the most significant address bits
are Don’t Care.
AI01442D
C
D
S
Q
A7
21 3 4 5 6 7 8 9 10111213141516171819
A6 A5 A4 A3 A2 A1 A0A8
20 21 22 23
High Impedance
Instruction Byte Address
0
765432 0
1
Data Byte