Datasheet
DocID6512 Rev 12 21/45
M950x0-W M950x0-R M950x0-DF Instructions
44
6.4 Write Status Register (WRSR)
A Write Status Register (WRSR) instruction allows new values to be written to the Status
register. Before it can be accepted, a Write Enable (WREN) instruction must previously have
been executed.
The WRSR instruction is entered by driving Chip Select (S) low, sending the instruction
code followed by the data byte on Serial Data input (D), and driving the Chip Select (
S)
signal high. Chip Select (
S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the WRSR instruction is not executed.
Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed write cycle that takes t
W
to complete (as specified in Table 16: DC characteristics
(M950x0-W, device grade 6) to Table 19: AC characteristics (M950x0-R or M95040-DF,
device grade 6)). The instruction sequence is shown in Figure 10: Write Status Register
(WRSR) sequence.
While the Write Status Register cycle is in progress, the Status register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed write
cycle t
W
, and, 0 when the write cycle is complete. The WEL bit (Write enable latch) is also
reset at the end of the write cycle t
W
.
The WRSR instruction allows the user to change the values of the BP1, BP0 bits which
define the size of the area that is to be treated as read only, as defined in
Table 3: Write-
protected block size. The contents of the BP1, BP0 bits are updated after the completion of
the WRSR instruction, including the t
W
write cycle.
The WRSR instruction has no effect on the b7, b6, b5, b4, b1 and b0 bits in the Status
register which are always read as 0.
Figure 10. Write Status Register (WRSR) sequence
The WRSR instruction is not accepted, and is not executed, under the following conditions:
if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before)
if a write cycle is already in progress
if the device has not been deselected, by Chip Select (S
) being driven high, after the
eighth bit, b0, of the data byte has been latched in
if Write Protect (W
) is low during the WRSR command (instruction, address and data)
C
D
AI01445B
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB