Datasheet

DocID5124 Rev 6 17/37
M93S46-W M93S56-W M93S66-W Instructions
5.3 Write to memory array (WRITE)
The Write Data to Memory instruction is composed of the Start bit plus the op-code followed
by the address and the 16 data bits to be written.
Write Enable (W) must be held High before and during the instruction. Input address and
data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or
after this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed.
While the M93Sx6 is performing a write cycle, but after a delay (t
SLSH
) before the status
information becomes available, Chip Select Input (S) can be driven High to monitor the
status of the write cycle.
Serial Data Output (Q) is driven Low while the M93Sx6 is still busy, and High when the cycle
is complete, and the M93Sx6 is ready to receive a new instruction. The M93Sx6 ignores any
data on the bus while it is busy on a write cycle. Once the M93Sx6 is Ready, Serial Data
Output (Q) is driven High, and remains in this state until a new start bit is decoded or the
Chip Select Input (S) is brought Low.
Programming is internally self-timed, so the external Serial Clock (C) may be disconnected
or left running after the start of a write cycle.
5.4 Page write
A Page Write to Memory (PAWRITE) instruction contains the first address to be written,
followed by up to 4 data words. After the receipt of each data word, bits A1-A0 of the internal
address counter are incremented, the high order bits remaining unchanged (A7-A2 for
M93S66, M93S56; A5-A2 for M93S46). Users must take care, in the software, to ensure
that the last word address has the same upper order address bits as the initial address
transmitted to avoid address roll-over.
The Page Write to Memory (PAWRITE) instruction will not be executed if any of the 4 words
addresses the protected area.
Write Enable (W) must be held High before and during the instruction. Input address and
data, on Serial Data Input (D) are sampled on the rising edge of Serial Clock (C).
After the last data bit has been sampled, the Chip Select Input (S) must be taken Low before
the next rising edge of Serial Clock (C). If Chip Select Input (S) is brought Low before or
after this specific time frame, the self-timed programming cycle will not be started, and the
addressed location will not be programmed.
While the M93Sx6 is performing a write cycle, but after a delay (t
SLSH
) before the status
information becomes available, Chip Select Input (S) can be driven High to monitor the
status of the write cycle. Serial Data Output (Q) is driven Low while the M93Sx6 is still busy,
and High when the cycle is complete, and the M93Sx6 is ready to receive a new instruction.
The M93Sx6 ignores any data on the bus while it is busy on a write cycle. Once the M93Sx6
is Ready, Serial Data Output (Q) is driven High, and remains in this state until a new start bit
is decoded or the Chip Select Input (S) is brought Low.
Programming is internally self-timed, so the external Serial Clock (C) may be disconnected
or left running after the start of a write cycle.