Datasheet

DocID5124 Rev 6 11/37
M93S46-W M93S56-W M93S66-W Clock pulse counter
4 Clock pulse counter
In a noisy environment, the number of pulses received on Serial Clock (C) may be greater
than the number delivered by the Bus Master (the micro- controller). This can lead to a
misalignment of the instruction of one or more bits (as shown in
Figure 3.) and may lead to
the writing of erroneous data at an erroneous address.
To combat this problem, the M93Sx6 has an on- chip counter that counts the clock pulses
from the start bit until the falling edge of the Chip Select Input (S). If the number of clock
pulses received is not the number expected, the WRITE, PAWRITE, WRALL, PRWRITE or
PRCLEAR instruction isaborted, and the contents of the memory are not modified.
The number of clock cycles expected for each in- struction, and for each member of the
M93Sx6 family, are summarized in
Table 2 and Table 3. For example, a Write Data to
Memory (WRITE) instruction on the M93S56 (or M93S66) expects 27 clock cycles from the
start bit to the falling edge of Chip Select Input (S). That is:
1 Start bit
+ 2 Op-code bits
+ 8 Address bits
+ 16 Data bits
Figure 3. Write sequence with one clock glitch
AI01395
S
An-1
C
D
WRITE
START
D0"1""0"
An
Glitch
An-2
ADDRESS AND DATA
ARE SHIFTED BY ONE BIT