Datasheet

Operating features M93S46-W M93S56-W M93S66-W
10/37 DocID5124 Rev 6
3 Operating features
The device is compatible with the MICROWIRE protocol. All instructions, addresses and
input data bytes are shifted into the device, most significant bit first. The Serial Data Input
(D) is sampled on the first rising edge of the Serial Clock (C) after Chip Select (S) goes high.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the rising edge of the Serial Clock (C) after the read instruction has
been clocked into the device.
The M93Sx6 is accessed by a set of instructions which includes Read, Write, Page Write,
Write All and instructions used to set the memory protection. These are summarized in
Table 2 and Table 3).
A Read Data from Memory (READ) instruction loads the address of the first word to be read
into an internal address counter. The data contained at this address is then clocked out
serially. The address counter is automatically incremented after the data is output and, if the
Chip Select Input (S) is held High, the M93Sx6 can output a sequential stream of data
words. In this way, the memory can be read as a data stream, or continuously as the
address counter automatically rolls over to 00h when the highest address is reached.
Writing data is internally self-timed (the external clock signal on Serial Clock (C) may be
stopped or left running after the start of a Write cycle) and does not require an erase cycle
prior to the Write instruction. The Write instruction writes 16 bits at a time into one of the
word locations of the M93Sx6, the Page Write instruction writes up to 4 words of 16 bits to
sequential locations, assuming in both cases that all addresses are outside the Write
Protected area.
Up to 4 words may be written with help of the Page Write instruction and the whole memory
may also be erased, or written to a predetermined pattern by using the Write All instruction,
within the time required by a write cycle (tW).
After the start of the write cycle, a Busy/Ready signal is available on Serial Data Output (Q)
when Chip Select Input (S) is driven High.
Within the memory, a user defined area may be protected against further Write instructions.
The size of this area is defined by the content of a Protection Register, located outside of the
memory array.
As a final protection step, data in this user defined area may be permanently protected by
programming a One Time Programming bit (OTP bit) which locks the Protection Register
content.