Datasheet

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M93S46-W M93S56-W M93S66-W DC and AC parameters
Table 11. AC Characteristics (M93Sx6-W, device grade 6)
Test conditions specified in Table 5 and Table 6
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SK
Clock frequency D.C. 2 MHz
t
PRVCH
t
PRES
Protect enable valid to clock high 50 - ns
t
WVCH
t
PES
Write enable valid to clock high 50 - ns
t
CLPRX
t
PREH
Clock low to protect enable transition 0 - ns
t
SLWX
t
PEH
Chip select low to write enable transition 250 - ns
t
SLCH
Chip select low to clock high 50 - ns
t
SHCH
t
CSS
Chip select set-up time 50 - ns
t
SLSH
(1)
t
CS
Chip select low to chip select high 200 - ns
t
CHCL
(2)
t
SKH
Clock high time 200 - ns
t
CLCH
(2)
t
SKL
Clock low time 200 - ns
t
DVCH
t
DIS
Data in set-up time 50 - ns
t
CHDX
t
DIH
Data in hold time 50 - ns
t
CLSH
t
SKS
Clock set-up time (relative to S) 50 - ns
t
CLSL
t
CSH
Chip select hold time 0 - ns
t
SHQV
t
SV
Chip select to ready/busy status - 200 ns
t
SLQZ
t
DF
Chip Select low to output Hi-Z - 100 ns
t
CHQL
t
PD0
Delay to output low - 200 ns
t
CHQV
t
PD1
Delay to output valid - 200 ns
t
W
t
WP
Erase/Write cycle time - 5 ms
1. Chip Select Input (S) must be brought Low for a minimum of t
SLSH
between consecutive instruction cycles.
2. t
CHCL
+ t
CLCH
≥ 1 / f
C
.