Datasheet

M93C86, M93C76, M93C66, M93C56, M93C46
22/31
Table 23. AC Characteristics (M93Cx6-R)
Note: 1. t
CHCL
+ t
CLCH
≥ 1 / f
C
.
2. Chip Select Input (S) must be brought Low for a minimum of t
SLSH
between consecutive instruction cycles.
3. This product is under development. For more information, please contact your nearest ST sales office.
Test conditions specified in Table 13. and Table 11.
Symbol Alt. Parameter
Min.
(3)
Max.
(3)
Unit
f
C
f
SK
Clock Frequency D.C. 1 MHz
t
SLCH
Chip Select Low to Clock High 250 ns
t
SHCH
t
CSS
Chip Select Set-up Time 50 ns
t
SLSH
(2)
t
CS
Chip Select Low to Chip Select High 250 ns
t
CHCL
(1)
t
SKH
Clock High Time 250 ns
t
CLCH
(1)
t
SKL
Clock Low Time 250 ns
t
DVCH
t
DIS
Data In Set-up Time 100 ns
t
CHDX
t
DIH
Data In Hold Time 100 ns
t
CLSH
t
SKS
Clock Set-up Time (relative to S) 100 ns
t
CLSL
t
CSH
Chip Select Hold Time 0 ns
t
SHQV
t
SV
Chip Select to Ready/Busy Status 400 ns
t
SLQZ
t
DF
Chip Select Low to Output Hi-Z 200 ns
t
CHQL
t
PD0
Delay to Output Low 400 ns
t
CHQV
t
PD1
Delay to Output Valid 400 ns
t
W
t
WP
Erase/Write Cycle time 10 ms