Datasheet

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M93C86, M93C76, M93C66, M93C56, M93C46
Table 22. AC Characteristics (M93Cx6-W, Device Grade 7 or 3)
Note: 1. t
CHCL
+ t
CLCH
≥ 1 / f
C
.
2. Chip Select Input (S) must be brought Low for a minimum of t
SLSH
between consecutive instruction cycles.
Test conditions specified in Table 13. and Table 10.
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SK
Clock Frequency D.C. 2 MHz
t
SLCH
Chip Select Low to Clock High 50 ns
t
SHCH
t
CSS
Chip Select Set-up Time 50 ns
t
SLSH
(2)
t
CS
Chip Select Low to Chip Select High 200 ns
t
CHCL
(1)
t
SKH
Clock High Time 200 ns
t
CLCH
(1)
t
SKL
Clock Low Time 200 ns
t
DVCH
t
DIS
Data In Set-up Time 50 ns
t
CHDX
t
DIH
Data In Hold Time 50 ns
t
CLSH
t
SKS
Clock Set-up Time (relative to S) 50 ns
t
CLSL
t
CSH
Chip Select Hold Time 0 ns
t
SHQV
t
SV
Chip Select to Ready/Busy Status 200 ns
t
SLQZ
t
DF
Chip Select Low to Output Hi-Z 100 ns
t
CHQL
t
PD0
Delay to Output Low 200 ns
t
CHQV
t
PD1
Delay to Output Valid 200 ns
t
W
t
WP
Erase/Write Cycle time 5 ms