Datasheet

M48T58, M48T58Y READ mode
Doc ID 2412 Rev 8 9/33
3 READ mode
The M48T58/Y is in the READ mode whenever W (WRITE enable) is high, E1 (chip enable
1) is low, and E2 (chip enable 2) is high. The unique address specified by the 13 address
inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be
available at the data I/O pins within address access time (t
AVQV
) after the last address input
signal is stable, providing that the E1
, E2, and G access times are also satisfied. If the E1,
E2 and G
access times are not met, valid data will be available after the latter of the chip
enable access times (t
E1LQV
or t
E2HQV
) or output enable access time (t
GLQV
).
The state of the eight three-state data I/O signals is controlled by E1
, E2 and G. If the
outputs are activated before t
AVQV
, the data lines will be driven to an indeterminate state
until t
AVQV
. If the address inputs are changed while E1, E2 and G remain active, output data
will remain valid for output data hold time (t
AXQX
) but will go indeterminate until the next
address access.
Figure 5. READ mode AC waveforms
Note: WRITE enable (W
) = high.
AI00962
tAVAV
tAVQV tAXQX
tE1LQV
tE1LQX
tE1HQZ
tGLQV
tGLQX
tGHQZ
VALID
A0-A12
E1
G
DQ0-DQ7
tE2HQV
tE2HQX
VALID
tE2LQZ
E2