Datasheet

Data retention mode M48T58, M48T58Y
14/33 Doc ID 2412 Rev 8
5 Data retention mode
With valid V
CC
applied, the M48T58/Y operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V
CC
falls within the V
PFD
(max), V
PFD
(min) window. All outputs
become high impedance, and all inputs are treated as “don't care.”
Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
PFD
(min), the
user can be assured the memory will be in a write protected state, provided the V
CC
fall time
is not less than t
F
. The M48T58/Y may respond to transient noise spikes on V
CC
that reach
into the deselect window during the time the device is sampling V
CC
. Therefore, decoupling
of the power supply lines is recommended.
When V
CC
drops below V
SO
, the control circuit switches power to the internal battery which
preserves data and powers the clock. The internal button cell will maintain data in the
M48T58/Y for an accumulated period of at least 7 years when V
CC
is less than V
SO
. As
system power returns and V
CC
rises above V
SO
, the battery is disconnected, and the power
supply is switched to external V
CC
. Write protection continues until V
CC
reaches V
PFD
(min)
plus t
rec
(min). E1 should be kept high or E2 low as V
CC
rises past V
PFD
(min) to prevent
inadvertent WRITE cycles prior to system stabilization. Normal RAM operation can resume
t
rec
after V
CC
exceeds V
PFD
(max).
For more information on battery storage life refer to the application note AN1012.