M48T37Y M48T37V 5.0 or 3.3 V, 256 Kbit (32 Kbit x 8) TIMEKEEPER® SRAM Features ■ Integrated ultra low power SRAM, real-time clock, power-fail control circuit, and battery ■ Frequency test output for real-time clock software calibration ■ Automatic power-fail chip deselect and WRITE protection ■ Watchdog timer ■ WRITE protect voltage (VPFD = Power-fail deselect voltage): – M48T37Y: VCC = 4.5 to 5.5 V 4.2 V ≤ VPFD ≤ 4.5 V – M48T37V: VCC = 3.0 to 3.6 V 2.7 V ≤ VPFD ≤ 3.
Contents M48T37Y, M48T37V Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 2.1 READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.
M48T37Y, M48T37V List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of figures M48T37Y, M48T37V List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. 4/30 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SOIC connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M48T37Y, M48T37V 1 Description Description The M48T37Y/V TIMEKEEPER® RAM is a 32 Kb x 8 non-volatile static RAM and real-time clock. The monolithic chip is available in a special package which provides a highly integrated battery-backed memory and real-time clock solution. The 44-lead, 330 mil SOIC package provides sockets with gold-plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal.
Description M48T37Y, M48T37V Table 1. Signal names A0-A14 Address inputs DQ0-DQ7 Data inputs / outputs RST Reset output (open drain) IRQ/FT Interrupt / frequency test output (open drain) WDI Watchdog input E Chip enable G Output enable W WRITE enable VCC Supply voltage VSS Ground NC Not connected internally Figure 2.
M48T37Y, M48T37V Figure 3.
Operation modes 2 M48T37Y, M48T37V Operation modes As Figure 3 on page 7 shows, the static memory array and the quartz controlled clock oscillator of the M48T37Y/V are integrated on one silicon chip. The memory locations that provide user accessible BYTEWIDE™ clock information are in the bytes with addresses 7FF1 and 7FF9h-7FFFh (located in Table 5 on page 13). The clock locations contain the century, year, month, date, day, hour, minute, and second in 24-hour BCD format.
M48T37Y, M48T37V Operation modes met, valid data will be available after the latter of the chip enable access time (tELQV) or output enable access time (tGLQV). The state of the eight three-state data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV.
Operation modes 2.2 M48T37Y, M48T37V WRITE mode The M48T37Y/V is in the WRITE mode whenever W and E are low. The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from chip enable or tWHAX from WRITE enable prior to the initiation of another READ or WRITE cycle.
M48T37Y, M48T37V Table 4.
Clock operations 3 Clock operations 3.1 Reading the clock M48T37Y, M48T37V Updates to the TIMEKEEPER® registers should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ bit, D6 in the control register 7FF8h.
M48T37Y, M48T37V Table 5.
Clock operations 3.4 M48T37Y, M48T37V Setting the alarm clock Registers 7FF5h-7FF2h contain the alarm settings. The alarm can be configured to go off at a predetermined time on a specific day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the M48T37Y/V is in the battery backup mode of operation to serve as a system wake-up call. RPT1-RPT4 put the alarm in the repeat mode of operation. Table 6 shows the possible configurations.
M48T37Y, M48T37V Figure 8. Clock operations Backup mode alarm waveforms tREC VCC VPFD (max) VPFD (min) VSO ABE, AFE bit in Interrupt Register AF bit in Flags Register IRQ/FT HIGH-Z HIGH-Z AI03254B 3.5 Calibrating the clock The M48T37Y/V is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed ±35 ppm (parts per million) oscillator frequency error at 25 °C, which equates to about ±1.53 minutes per month.
Clock operations M48T37Y, M48T37V Two methods are available for ascertaining how much calibration a given M48T37Y/V may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWW broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure.
M48T37Y, M48T37V Clock operations The watchdog timer is disabled by writing a value of 00000000 to the eight bits in the watchdog register. Should the watchdog timer time out, a value of 00h needs to be written to the watchdog register in order to clear the IRQ/FT pin. The watchdog function is automatically disabled upon power-down and the watchdog register is cleared.
Clock operations 3.9 M48T37Y, M48T37V Battery low flag The M48T37Y/V automatically performs periodic battery voltage monitoring upon power-up. The battery low flag (BL), bit D4 of the flags register 7FF0h, will be asserted high if the SNAPHAT® battery is found to be less than approximately 2.5 V. The BL flag will remain active until completion of battery replacement and subsequent battery low monitoring tests during the next power-up sequence.
M48T37Y, M48T37V Clock operations one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 9. Supply voltage protection VCC VCC 0.1µF DEVICE VSS AI02169 Figure 10.
Maximum ratings 4 M48T37Y, M48T37V Maximum ratings Stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 8.
M48T37Y, M48T37V 5 DC and AC parameters DC and AC parameters This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC characteristic tables are derived from tests performed under the measurement conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 9.
DC and AC parameters Table 11. M48T37Y, M48T37V DC characteristics Symbol Parameter M48T37Y M48T37V –70 –100 Test condition(1) Min ILI(2) ILO (3) Input leakage current Output leakage current Max Min Unit Max 0 V ≤ VIN ≤ VCC ±1 ±1 µA 0 V ≤ VOUT ≤ VCC ±1 ±1 µA Outputs open 50 33 mA E = VIH 3 2 mA E = VCC – 0.2 V 3 2 mA ICC Supply current ICC1 Supply current (standby) TTL ICC2 Supply current (standby) CMOS VIL Input low voltage –0.3 0.8 –0.3 0.
M48T37Y, M48T37V Table 12. DC and AC parameters Power down/up AC characteristics Parameter(1) Symbol Min Max Unit tF(2) VPFD (max) to VPFD (min) VCC fall time 300 µs tFB(3) VPFD (min) to VSS VCC fall time 10 µs VPFD (min) to VPFD (max) VCC rise time 10 µs VSS to VPFD (min) VCC rise time 1 µs VPFD (max) to RST high 40 tR tRB tREC (4) 200 ms 1. Valid for ambient operating temperature: TA = 0 to 70 °C or –40 to 85 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted). 2.
Package mechanical data 6 M48T37Y, M48T37V Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 14.
M48T37Y, M48T37V Package mechanical data Figure 15. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, pack. outline A1 A2 A A3 eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 15. SH – 4-pin SNAPHAT® housing for 48 mAh battery & crystal, package mechanical data mm inches Symbol Typ Min A Max Typ Min 9.78 Max 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 B 0.38 0.46 0.56 0.015 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.
Package mechanical data M48T37Y, M48T37V Figure 16. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, pack. outline A1 A2 A A3 eA B L eB D E SHTK-A Note: Drawing is not to scale. Table 16. SH – 4-pin SNAPHAT® housing for 120 mAh battery & crystal, package mechanical data mm inches Symbol Typ Min A Typ Min 10.54 Max 0.415 A1 8.00 8.51 0.315 .0335 A2 7.24 8.00 0.285 0.315 A3 26/30 Max 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.
M48T37Y, M48T37V 7 Part numbering Part numbering Table 17. Ordering information scheme Example: M48T 37Y –70 MH 1 E Device type M48T Supply voltage and write protect voltage 37Y = VCC = 4.5 to 5.5 V; VPFD = 4.2 to 4.5 V 37V = VCC = 3.0 to 3.6 V; VPFD = 2.7 to 3.
Environmental information 8 M48T37Y, M48T37V Environmental information Figure 17. Recycling symbols This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. Recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations.
M48T37Y, M48T37V 9 Revision history Revision history Table 19. Document revision history Date Revision Changes Dec-1999 1 First issue 07-Feb-2000 2 From preliminary data to datasheet; battery low flag paragraph changed; 100 ns speed class identifier changed (Table , 4) 11-Jul-2000 2.1 19-Jun-2001 3 06-Aug-2001 3.1 Fix text for setting the alarm clock (Figure 7) 15-Jan-2002 3.2 Fix footnote numbering (Table ) 20-May-2002 3.
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