Datasheet

Clock operation M48T201Y, M48T201V
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3.8 Power-on reset
The M48T201Y/V continuously monitors V
CC
. When V
CC
falls to the power fail detect trip
point, the RST
pulls low (open drain) and remains low on power-up for t
REC
after V
CC
passes V
PFD
(max). The RST pin is an open drain output and an appropriate pull-up resistor
to V
CC
should be chosen to control rise time.
3.9 Reset inputs (RSTIN1 & RSTIN2)
The M48T201Y/V provides two independent inputs which can generate an output reset. The
duration and function of these resets is identical to a reset generated by a power cycle.
Figure 9 and Table 8 illustrate the AC reset characteristics of this function. Pulses shorter
than t
R1
and t
R2
will not generate a reset condition. RSTIN1 and RSTIN2 are each internally
pulled up to V
CC
through a 100 KΩ resistor.
Figure 9. RSTIN1
and RSTIN2 timing waveforms
Table 8. Reset AC characteristics
3.10 Calibrating the clock
The M48T201Y/V is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are factory calibrated at 25°C and tested for accuracy. Clock
accuracy will not exceed ±35 ppm (parts per million) oscillator frequency error at 25°C,
which equates to about ±1.53 minutes per month. When the calibration circuit is properly
employed, accuracy improves to better than +1/–2 ppm at 25°C.
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= 0 to 70°C; V
CC
= 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
Min Max Unit
t
R1
RSTIN1 low to RST low 50 200 ns
t
R2
RSTIN2 low to RST low 20 100 ms
t
R1HRZ
(2)
2. C
L
= 5 pF (see Figure 13 on page 28).
RSTIN1 high to RST Hi-Z 40 200 ms
t
R2HRZ
(2)
RSTIN2 high to RST Hi-Z 40 200 ms
AI01679
RSTIN1
RST
RSTIN2
tR1 tR1HRZ
Hi-Z
tR2
tR2HRZ
Hi-Z