Datasheet

M48T201Y, M48T201V Clock operation
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In order to perform a software reset of the watchdog timer, the original timeout period can be
written into the watchdog register, effectively restarting the countdown cycle.
Should the watchdog timer time out, and the WDS bit is programmed to output an interrupt,
a value of 00h needs to be written to the watchdog register in order to clear the IRQ
/FT pin.
This will also disable the watchdog function until it is again programmed correctly. A READ
of the flags register will reset the watchdog flag (bit D7; register 7FFF0h).
The watchdog function is automatically disabled upon power-down and the watchdog
register is cleared. If the watchdog function is set to output to the IRQ
/FT pin and the
frequency test function is activated, the watchdog or alarm function prevails and the
frequency test function is denied.
Note: The user must transition the address (or toggle chip enable) to see the flag bit change.
3.7 Square wave output
The M48T201Y/V offers the user a programmable square wave function which is output on
the SQW pin. RS3-RS0 bits located in 7FFF0h establish the square wave output frequency.
These frequencies are listed in Tab le 7 . Once the selection of the SQW frequency has been
completed, the SQW pin can be turned on and off under software control with the square
wave enable bit (SQWE) located in register 7FFF6h.
Table 7. Square wave output frequency
Square wave bits Square wave
RS3RS2RS1RS0FrequencyUnits
0000Hi-Z-
0 0 0 1 32.768 kHz
00108.192kHz
00114.096kHz
01002.048kHz
01011.024kHz
0110512Hz
0111256Hz
1000128Hz
100164Hz
101032Hz
101116Hz
11008Hz
11014Hz
11102Hz
11111Hz