Datasheet

M48T201Y, M48T201V Operation
11/37
Table 2. Operating modes
Note: X = V
IH
or V
IL
; V
SO
= battery backup switchover voltage
2.2 Read mode
The M48T201Y/V executes a READ cycle whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the address inputs (A0-A18) defines which
one of the on-chip TIMEKEEPER
®
registers or external SRAM locations is to be accessed.
When the address presented to the M48T201Y/V is in the range of 7FFFFh-7FFF0h, one of
the on-board TIMEKEEPER registers is accessed and valid data will be available to the
eight data output drivers within t
AVQV
after the address input signal is stable, providing that
the E
and G access times are also satisfied. If they are not, then data access must be
measured from the latter occurring signal (E
or G) and the limiting parameter is either t
ELQV
for E
or t
GLQV
for G rather than the address access time. When one of the on-chip
TIMEKEEPER registers is selected for READ, the G
CON
signal will remain inactive
throughout the READ cycle.
When the address value presented to the M48T201Y/V is outside the range of
TIMEKEEPER registers, an external SRAM location will be selected. In this case the G
signal will be passed to the G
CON
pin, with the specified delay times of t
AOEL
or t
OERL
.
Figure 4. G
CON
timing when switching between RTC and external SRAM
Mode V
CC
EGW
DQ7-
DQ0
Power
Deselect
4.5 V to 5.5 V
or
3.0 V to 3.6 V
V
IH
X X High-Z Standby
WRITE V
IL
XV
IL
D
IN
Active
READ V
IL
V
IL
V
IH
D
OUT
Active
READ V
IL
V
IH
V
IH
High-Z Active
Deselect V
SO
to V
PFD
(min)
(1)
1. See Table 14 on page 30 for details.
X X X High-Z CMOS standby
Deselect ≤ V
SO
(1)
X X X High-Z Battery backup
AI02333
G
E
G
CON
tAOEL
ADDRESS
00000h - 7FFEFh 7FFF0h - 7FFFFh 00000h - 7FFEFh7FFF0h - 7FFFFh
tAOEH
tOERL
tRO
External SRAM
RTC
External SRAM
RTC