Datasheet

M48T02, M48T12 Operation modes
Doc ID 2410 Rev 9 9/25
2.2 WRITE mode
The M48T02/12 is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W
or E. A WRITE is terminated by the
earlier rising edge of W
or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
EHAX
from chip enable or t
WHAX
from WRITE enable prior
to the initiation of another READ or WRITE cycle. Data-in must be valid t
DVWH
prior to the
end of WRITE and remain valid for t
WHDX
afterward. G should be kept high during WRITE
cycles to avoid bus contention; although, if the output bus has been activated by a low on E
and G
, a low on W will disable the outputs t
WLQZ
after W falls.
Figure 5. WRITE enable controlled, WRITE AC waveform
Figure 6. Chip enable controlled, WRITE AC waveforms
AI01331
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A10
E
W
DQ0-DQ7
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
AI01332B
tAVAV
tEHAX
tDVEH
A0-A10
E
W
DQ0-DQ7
VALID
tAVEH
tAVEL
tAVWL
tELEH
tEHDX
DATA INPUT